#ifndef HW_PC_H #define HW_PC_H #include "exec/memory.h" #include "hw/boards.h" #include "hw/isa/isa.h" #include "hw/block/fdc.h" #include "hw/block/flash.h" #include "net/net.h" #include "hw/i386/ioapic.h" #include "qemu/range.h" #include "qemu/bitmap.h" #include "qemu/module.h" #include "sysemu/sysemu.h" #include "hw/pci/pci.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/acpi_dev_interface.h" #define HPET_INTCAP "hpet-intcap" /** * PCMachineState: * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling * @boot_cpus: number of present VCPUs * @smp_dies: number of dies per one package */ struct PCMachineState { /*< private >*/ MachineState parent_obj; /* */ /* State for other subsystems/APIs: */ Notifier machine_done; /* Pointers to devices and objects: */ HotplugHandler *acpi_dev; ISADevice *rtc; PCIBus *bus; FWCfgState *fw_cfg; qemu_irq *gsi; PFlashCFI01 *flash[2]; /* Configuration options: */ uint64_t max_ram_below_4g; OnOffAuto vmport; OnOffAuto smm; bool acpi_build_enabled; bool smbus_enabled; bool sata_enabled; bool pit_enabled; /* RAM information (sizes, addresses, configuration): */ ram_addr_t below_4g_mem_size, above_4g_mem_size; /* CPU and apic information: */ bool apic_xrupt_override; unsigned apic_id_limit; uint16_t boot_cpus; unsigned smp_dies; /* NUMA information: */ uint64_t numa_nodes; uint64_t *node_mem; /* Address space used by IOAPIC device. All IOAPIC interrupts * will be translated to MSI messages in the address space. */ AddressSpace *ioapic_as; }; #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size" #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" #define PC_MACHINE_VMPORT "vmport" #define PC_MACHINE_SMM "smm" #define PC_MACHINE_SMBUS "smbus" #define PC_MACHINE_SATA "sata" #define PC_MACHINE_PIT "pit" /** * PCMachineClass: * * Compat fields: * * @enforce_aligned_dimm: check that DIMM's address/size is aligned by * backend's alignment value if provided * @acpi_data_size: Size of the chunk of memory at the top of RAM * for the BIOS ACPI tables and other BIOS * datastructures. * @gigabyte_align: Make sure that guest addresses aligned at * 1Gbyte boundaries get mapped to host * addresses aligned at 1Gbyte boundaries. This * way we can use 1GByte pages in the host. * */ typedef struct PCMachineClass { /*< private >*/ MachineClass parent_class; /*< public >*/ /* Device configuration: */ bool pci_enabled; bool kvmclock_enabled; const char *default_nic_model; /* Compat options: */ /* Default CPU model version. See x86_cpu_set_default_version(). */ int default_cpu_version; /* ACPI compat: */ bool has_acpi_build; bool rsdp_in_ram; int legacy_acpi_table_size; unsigned acpi_data_size; /* SMBIOS compat: */ bool smbios_defaults; bool smbios_legacy_mode; bool smbios_uuid_encoded; /* RAM / address space compat: */ bool gigabyte_align; bool has_reserved_memory; bool enforce_aligned_dimm; bool broken_reserved_end; /* TSC rate migration: */ bool save_tsc_khz; /* generate legacy CPU hotplug AML */ bool legacy_cpu_hotplug; /* use DMA capable linuxboot option rom */ bool linuxboot_dma_enabled; /* use PVH to load kernels that support this feature */ bool pvh_enabled; /* Enables contiguous-apic-ID mode */ bool compat_apic_id_mode; } PCMachineClass; #define TYPE_PC_MACHINE "generic-pc-machine" #define PC_MACHINE(obj) \ OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE) #define PC_MACHINE_GET_CLASS(obj) \ OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE) #define PC_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE) /* i8259.c */ extern DeviceState *isa_pic; qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); qemu_irq *kvm_i8259_init(ISABus *bus); int pic_read_irq(DeviceState *d); int pic_get_output(DeviceState *d); /* ioapic.c */ /* Global System Interrupts */ #define GSI_NUM_PINS IOAPIC_NUM_PINS typedef struct GSIState { qemu_irq i8259_irq[ISA_NUM_IRQS]; qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; } GSIState; void gsi_handler(void *opaque, int n, int level); /* vmport.c */ #define TYPE_VMPORT "vmport" typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address); static inline void vmport_init(ISABus *bus) { isa_create_simple(bus, TYPE_VMPORT); } void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque); void vmmouse_get_data(uint32_t *data); void vmmouse_set_data(const uint32_t *data); /* pc.c */ extern int fd_bootchk; bool pc_machine_is_smm_enabled(PCMachineState *pcms); void pc_register_ferr_irq(qemu_irq irq); void pc_acpi_smi_interrupt(void *opaque, int irq, int level); void pc_cpus_init(PCMachineState *pcms); void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp); void pc_smp_parse(MachineState *ms, QemuOpts *opts); void pc_guest_info_init(PCMachineState *pcms); #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, MemoryRegion *pci_address_space); void xen_load_linux(PCMachineState *pcms); void pc_memory_init(PCMachineState *pcms, MemoryRegion *system_memory, MemoryRegion *rom_memory, MemoryRegion **ram_memory); uint64_t pc_pci_hole64_start(void); qemu_irq pc_allocate_cpu_irq(void); DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, ISADevice **rtc_state, bool create_fdctrl, bool no_vmport, bool has_pit, uint32_t hpet_irqs); void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); void pc_cmos_init(PCMachineState *pcms, BusState *ide0, BusState *ide1, ISADevice *s); void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); void pc_pci_device_init(PCIBus *pci_bus); typedef void (*cpu_set_smm_t)(int smm, void *arg); void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); ISADevice *pc_find_fdc0(void); int cmos_get_fd_drive_type(FloppyDriveType fd0); #define FW_CFG_IO_BASE 0x510 #define PORT92_A20_LINE "a20" /* acpi_piix.c */ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, int smm_enabled, DeviceState **piix4_pm); /* hpet.c */ extern int no_hpet; /* piix_pci.c */ struct PCII440FXState; typedef struct PCII440FXState PCII440FXState; #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" #define TYPE_I440FX_PCI_DEVICE "i440FX" #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" /* * Reset Control Register: PCI-accessible ISA-Compatible Register at address * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). */ #define RCR_IOPORT 0xcf9 PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCII440FXState **pi440fx_state, int *piix_devfn, ISABus **isa_bus, qemu_irq *pic, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, ram_addr_t ram_size, ram_addr_t below_4g_mem_size, ram_addr_t above_4g_mem_size, MemoryRegion *pci_memory, MemoryRegion *ram_memory); PCIBus *find_i440fx(void); /* piix4.c */ extern PCIDevice *piix4_dev; int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); /* pc_sysfw.c */ void pc_system_flash_create(PCMachineState *pcms); void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); /* acpi-build.c */ void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, const CPUArchIdList *apic_ids, GArray *entry); /* e820 types */ #define E820_RAM 1 #define E820_RESERVED 2 #define E820_ACPI 3 #define E820_NVS 4 #define E820_UNUSABLE 5 int e820_add_entry(uint64_t, uint64_t, uint32_t); int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); extern GlobalProperty pc_compat_4_0[]; extern const size_t pc_compat_4_0_len; extern GlobalProperty pc_compat_3_1[]; extern const size_t pc_compat_3_1_len; extern GlobalProperty pc_compat_3_0[]; extern const size_t pc_compat_3_0_len; extern GlobalProperty pc_compat_2_12[]; extern const size_t pc_compat_2_12_len; extern GlobalProperty pc_compat_2_11[]; extern const size_t pc_compat_2_11_len; extern GlobalProperty pc_compat_2_10[]; extern const size_t pc_compat_2_10_len; extern GlobalProperty pc_compat_2_9[]; extern const size_t pc_compat_2_9_len; extern GlobalProperty pc_compat_2_8[]; extern const size_t pc_compat_2_8_len; extern GlobalProperty pc_compat_2_7[]; extern const size_t pc_compat_2_7_len; extern GlobalProperty pc_compat_2_6[]; extern const size_t pc_compat_2_6_len; extern GlobalProperty pc_compat_2_5[]; extern const size_t pc_compat_2_5_len; extern GlobalProperty pc_compat_2_4[]; extern const size_t pc_compat_2_4_len; extern GlobalProperty pc_compat_2_3[]; extern const size_t pc_compat_2_3_len; extern GlobalProperty pc_compat_2_2[]; extern const size_t pc_compat_2_2_len; extern GlobalProperty pc_compat_2_1[]; extern const size_t pc_compat_2_1_len; extern GlobalProperty pc_compat_2_0[]; extern const size_t pc_compat_2_0_len; extern GlobalProperty pc_compat_1_7[]; extern const size_t pc_compat_1_7_len; extern GlobalProperty pc_compat_1_6[]; extern const size_t pc_compat_1_6_len; extern GlobalProperty pc_compat_1_5[]; extern const size_t pc_compat_1_5_len; extern GlobalProperty pc_compat_1_4[]; extern const size_t pc_compat_1_4_len; /* Helper for setting model-id for CPU models that changed model-id * depending on QEMU versions up to QEMU 2.4. */ #define PC_CPU_MODEL_IDS(v) \ { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ { \ MachineClass *mc = MACHINE_CLASS(oc); \ optsfn(mc); \ mc->init = initfn; \ } \ static const TypeInfo pc_machine_type_##suffix = { \ .name = namestr TYPE_MACHINE_SUFFIX, \ .parent = TYPE_PC_MACHINE, \ .class_init = pc_machine_##suffix##_class_init, \ }; \ static void pc_machine_init_##suffix(void) \ { \ type_register(&pc_machine_type_##suffix); \ } \ type_init(pc_machine_init_##suffix) extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id); #endif