- 30 10月, 2015 1 次提交
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由 Yongbok Kim 提交于
Add Performance Counter (4) and XNP (5) register numbers to RDHWR. Add check_hwrena() to simplify access control checkings. Add RDHWR support to microMIPS R6. Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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- 18 9月, 2015 2 次提交
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由 Pavel Dovgaluk 提交于
This patch improves exception handling in MIPS. Instructions generate several types of exceptions. When exception is generated, it breaks the execution of the current translation block. Implementation of the exceptions handling does not correctly restore icount for the instruction which caused the exception. In most cases icount will be decreased by the value equal to the size of TB. This patch passes pointer to the translation block internals to the exception handler. It allows correct restoring of the icount value. Signed-off-by: NPavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: avoid retranslation in linux-user SC, break lines which are over 80 chars, remove v3 changelog from the commit message] Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Alex Smith 提交于
For RDHWR on the CP0.Count register, env->CP0_Count was being returned. This value is a delta against the QEMU_CLOCK_VIRTUAL clock, not the correct current value of CP0.Count. Use cpu_mips_get_count() instead. Signed-off-by: NAlex Smith <alex.smith@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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- 11 9月, 2015 1 次提交
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由 Benjamin Herrenschmidt 提交于
This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 13 8月, 2015 1 次提交
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由 Richard Henderson 提交于
There are now no unconditional uses of qemu_log in the subdirectory. Signed-off-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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- 28 7月, 2015 1 次提交
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由 Yongbok Kim 提交于
Correct computation of vector offsets for EXCP_EXT_INTERRUPT. For instance, if Cause.IV is 0 the vector offset should be 0x180. Simplify the finding vector number logic for the Vectored Interrupts. Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: cosmetic changes] Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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- 15 7月, 2015 2 次提交
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由 Leon Alrae 提交于
Fix Debug Mode flag clearing, and when DERET is placed between LL and SC do not make SC fail. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
When syncing the task ASID with EntryHi, correctly or the value instead of assigning it. Reported-by: N"Dr. David Alan Gilbert" <dgilbert@redhat.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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- 12 6月, 2015 3 次提交
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由 Leon Alrae 提交于
CP0.PageGrain.ELPA enables support for large physical addresses. This field is encoded as follows: 0: Large physical address support is disabled. 1: Large physical address support is enabled. If this bit is a 1, the following changes occur to coprocessor 0 registers: - The PFNX field of the EntryLo0 and EntryLo1 registers is writable and concatenated with the PFN field to form the full page frame number. - Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined. P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA is disabled (CP0.PageGrain.ELPA = 0) then assume 32-bit Address Mode. In MIPS64 assume 36 as default PABITS (when CP0.PageGrain.ELPA = 0). env->PABITS value is constant and indicates maximum PABITS available on a core, whereas env->PAMask is calculated from env->PABITS and is also affected by CP0.PageGrain.ELPA. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Leon Alrae 提交于
Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large physical address is not supported. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Leon Alrae 提交于
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32. Introduce gen_move_low32() function which moves low 32 bits from 64-bit temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on MIPS32. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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- 11 6月, 2015 3 次提交
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由 Leon Alrae 提交于
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed between an LL and SC sequence, will never cause the SC to fail. Presence of ERETNC is denoted by the Config5.LLB. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Yongbok Kim 提交于
MIPS SIMD Architecture vector loads and stores require misalignment support. MSA Memory access should work as an atomic operation. Therefore, it has to check validity of all addresses for a vector store access if it is spanning into two pages. Separating helper functions for each data format as format is known in translation. To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag. Removing save_cpu_state() call in translation because it is able to use cpu_restore_state() on fault as GETRA() is passed. Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: remove unused do_* functions] Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Leon Alrae 提交于
This relatively small architectural feature adds the following: FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are available. Config5.FRE: When enabled all single-precision FP arithmetic instructions, LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions exception. Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1 instructions. Enable the feature in MIPS64R6-generic CPU. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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- 13 2月, 2015 1 次提交
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由 Leon Alrae 提交于
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NMaciej W. Rozycki <macro@linux-mips.org>
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- 20 1月, 2015 1 次提交
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由 Peter Maydell 提交于
Use cpu_*_data instead of the direct *_raw load/store accessors. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1421334118-3287-9-git-send-email-peter.maydell@linaro.org
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- 16 12月, 2014 8 次提交
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由 Maciej W. Rozycki 提交于
Add missing calls to synchronise the SoftFloat status with the CP1.FSCR: + for the rounding and flush-to-zero modes upon processor reset, + for the flush-to-zero mode on FSCR updates through the GDB stub. Refactor code accordingly and remove the redundant RESTORE_ROUNDING_MODE macro. Signed-off-by: NThomas Schwinge <thomas@codesourcery.com> Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Maciej W. Rozycki 提交于
Make CP0.Status writes made with the MTTC0 instruction respect this register's mask just like all the other places. Also preserve the current values of masked out bits. Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Maciej W. Rozycki 提交于
Fix CP0.Config3.ISAOnExc write accesses on microMIPS processors. This bit is mandatory for any processor that implements the microMIPS instruction set. This bit is r/w for processors that implement both the standard MIPS and the microMIPS instruction set. This bit is r/o and hardwired to 1 if only the microMIPS instruction set is implemented. There is no other bit ever writable in CP0.Config3 so defining a corresponding `CP0_Config3_rw_bitmask' member in `CPUMIPSState' is I think an overkill. Therefore make the ability to write the bit rely on the presence of ASE_MICROMIPS set in the instruction flags. The read-only case of the microMIPS instruction set being implemented only can be added when we add support for such a configuration. We do not currently have such support, we have no instruction flag that would control the presence of the standard MIPS instruction set nor any associated code in instruction decoding. This change is needed to boot a microMIPS Linux kernel successfully, otherwise it hangs early on as interrupts are enabled and then the exception handler invoked loops as its first instruction is interpreted in the wrong execution mode and triggers another exception right away. And then over and over again. We already check the current setting of the CP0.Config3.ISAOnExc in `set_hflags_for_handler' to set the ISA bit correctly on the exception handler entry so it is the ability to set it that is missing only. Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Maciej W. Rozycki 提交于
Make writes to CP0.Status and CP0.Cause have the same effect as executing corresponding MTC0 instructions would in Kernel Mode. Also ignore writes in the user emulation mode. Currently for requests from the GDB stub we write all the bits across both registers, ignoring any read-only locations, and do not synchronise the environment to evaluate side effects. We also write these registers in the user emulation mode even though a real kernel presents them as read only. Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Maciej W. Rozycki 提交于
Correct these issues with the handling of CP0.Status for MIPSr6: * only ignore the bit pattern of 0b11 on writes to CP0.Status.KSU, that is for processors that do implement Supervisor Mode, let the bit pattern be written to CP0.Status.UM:R0 freely (of course the value written to read-only CP0.Status.R0 will be discarded anyway); this is in accordance to the relevant architecture specification[1], * check the newly written pattern rather than the current contents of CP0.Status for the KSU bits being 0b11, * use meaningful macro names to refer to CP0.Status bits rather than magic numbers. References: [1] "MIPS Architecture For Programmers, Volume III: MIPS64 / microMIPS64 Privileged Resource Architecture", MIPS Technologies, Inc., Document Number: MD00091, Revision 6.00, March 31, 2014, Table 9.45 "Status Register Field Descriptions", pp. 210-211. Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Maciej W. Rozycki 提交于
Restore the order of helpers that used to be: unary operations (generic, then MIPS-specific), binary operations (generic, then MIPS-specific), compare operations. At one point FMA operations were inserted at a random place in the file, disregarding the preexisting order, and later on even more operations sprinkled across the file. Revert the mess by moving FMA operations to a new ternary class inserted after the binary class and move the misplaced unary and binary operations to where they belong. Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Maciej W. Rozycki 提交于
Remove the `FLOAT_OP' macro, unused since commit b6d96bed [Use temporary registers for the MIPS FPU emulation.]. Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Maciej W. Rozycki 提交于
Move the call to `update_fcr31' in `helper_float_cvtw_s' after the exception flag check, for consistency with the remaining helpers that do it last too. Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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- 03 11月, 2014 8 次提交
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由 Yongbok Kim 提交于
add MSA MI10 format instructions update LSA and DLSA for MSA add 16, 64 bit load and store Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Yongbok Kim 提交于
Remove the duplicated ieee_rm in gdbstub.c. Make the other ieee_rm and ieee_ex_to_mips available to other files. Reviewed-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com> Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Yongbok Kim 提交于
add defines and data structure for MIPS SIMD Architecture Reviewed-by: NJames Hogan <james.hogan@imgtec.com> Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Leon Alrae 提交于
In Release 6 not all the values are allowed to be written to a register. If the value is not valid or unsupported then it should stay unchanged. For pre-R6 the existing behaviour has been changed only for CP0_Index register as the current implementation does not seem to be correct - it looks like it tries to limit the input value but the limit is higher than the actual number of tlb entries. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NYongbok Kim <yongbok.kim@imgtec.com>
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由 Leon Alrae 提交于
BadInstr Register (CP0 Register 8, Select 1) The BadInstr register is a read-only register that capture the most recent instruction which caused an exception. BadInstrP Register (CP0 Register 8, Select 2) The BadInstrP register contains the prior branch instruction, when the faulting instruction is in a branch delay slot. Using error_code to indicate whether AdEL or TLBL was triggered during instruction fetch, in this case BadInstr is not updated as valid instruction word is not available. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NYongbok Kim <yongbok.kim@imgtec.com>
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由 Leon Alrae 提交于
For Standard TLB configuration (Config.MT=1): TLBINV invalidates a set of TLB entries based on ASID. The virtual address is ignored in the entry match. TLB entries which have their G bit set to 1 are not modified. TLBINVF causes all entries to be invalidated. Single TLB entry can be marked as invalid on TLB entry write by having EntryHi.EHINV set to 1. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NYongbok Kim <yongbok.kim@imgtec.com>
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由 Leon Alrae 提交于
PageGrain needs rw bitmask which differs between MIPS architectures. In pre-R6 if RIXI is supported, PageGrain.XIE and PageGrain.RIE are writeable, whereas in R6 they are read-only 1. On MIPS64 mtc0 instruction left shifts bits 31:30 for MIPS32 backward compatiblity, therefore there are separate mtc0 and dmtc0 helpers. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NYongbok Kim <yongbok.kim@imgtec.com>
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由 Leon Alrae 提交于
In Revision 3 of the architecture, the RI and XI bits were added to the TLB to enable more secure access of memory pages. These bits (along with the Dirty bit) allow the implementation of read-only, write-only, no-execute access policies for mapped pages. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NYongbok Kim <yongbok.kim@imgtec.com>
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- 24 10月, 2014 1 次提交
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由 Leon Alrae 提交于
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Message-id: 1413982829-27225-1-git-send-email-leon.alrae@imgtec.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 14 10月, 2014 3 次提交
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由 Peter Maydell 提交于
The do_lbu() function defined by the expansion of HELPER_LD() is never used, so don't define it. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Yongbok Kim 提交于
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Leon Alrae 提交于
In terms of encoding MIPS32R6 MIN.fmt, MAX.fmt, MINA.fmt, MAXA.fmt replaced MIPS-3D RECIP1, RECIP2, RSQRT1, RSQRT2 instructions. In R6 all Floating Point instructions are supposed to be IEEE-2008 compliant i.e. FIR.HAS2008 always 1. However, QEMU softfloat for MIPS has not been updated yet. Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NYongbok Kim <yongbok.kim@imgtec.com>
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- 13 10月, 2014 1 次提交
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由 Yongbok Kim 提交于
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
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- 07 8月, 2014 1 次提交
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由 James Hogan 提交于
MIPS registers an unassigned access handler which raises a guest bus error exception. However this causes QEMU to crash when KVM is enabled as it isn't called from the main execution loop so longjmp() gets called without a corresponding setjmp(). Until the KVM API can be updated to trigger a guest exception in response to an MMIO exit, prevent the bus error exception being raised from mips_cpu_unassigned_access() if KVM is enabled. The check is at run time since the do_unassigned_access callback is initialised before it is known whether KVM will be enabled. The problem can be triggered with Malta emulation by making the guest write to the reset region at physical address 0x1bf00000, since it is marked read-only which is treated as unassigned for writes. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@redhat.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 19 6月, 2014 1 次提交
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由 Petar Jovanovic 提交于
From MIPS documentation (Volume III): UserLocal Register (CP0 Register 4, Select 2) Compliance Level: Recommended. The UserLocal register is a read-write register that is not interpreted by the hardware and conditionally readable via the RDHWR instruction. This register only exists if the Config3-ULRI register field is set. Privileged software may write this register with arbitrary information and make it accessible to unprivileged software via register 29 (ULR) of the RDHWR instruction. To do so, bit 29 of the HWREna register must be set to a 1 to enable unprivileged access to the register. Signed-off-by: NPetar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 05 6月, 2014 1 次提交
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由 Paolo Bonzini 提交于
This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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