1. 22 8月, 2011 1 次提交
  2. 08 8月, 2011 1 次提交
  3. 21 2月, 2011 1 次提交
  4. 12 2月, 2011 1 次提交
  5. 12 12月, 2010 1 次提交
  6. 11 12月, 2010 1 次提交
  7. 22 5月, 2010 1 次提交
  8. 22 3月, 2010 1 次提交
  9. 02 10月, 2009 2 次提交
  10. 10 9月, 2009 3 次提交
  11. 28 8月, 2009 4 次提交
  12. 11 8月, 2009 1 次提交
  13. 10 7月, 2009 1 次提交
  14. 01 11月, 2008 1 次提交
    • A
      Make DMA bottom-half driven (v2) · 492c30af
      aliguori 提交于
      The current DMA routines are driven by a call in main_loop_wait() after every
      select.
      
      This patch converts the DMA code to be driven by a constantly rescheduled
      bottom half.  The advantage of using a scheduled bottom half is that we can
      stop scheduling the bottom half when there no DMA channels are runnable.  This
      means we can potentially detect this case and sleep longer in the main loop.
      
      The only two architectures implementing DMA_run() are cris and i386.  For cris,
      I converted it to a simple repeating bottom half.  I've only compile tested
      this as cris does not seem to work on a 64-bit host.  It should be functionally
      identical to the previous implementation so I expect it to work.
      
      For x86, I've made sure to only fire the DMA bottom half if there is a DMA
      channel that is runnable.  The effect of this is that unless you're using sb16
      or a floppy disk, the DMA bottom half never fires.
      
      You probably should test this malc.  My own benchmarks actually show slight
      improvement by it's possible the change in timing could affect your demos.
      
      Since v1, I've changed the code to use a BH instead of a timer.  cris at least
      seems to depend on faster than 10ms polling.
      Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      
      
      
      git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5573 c046a42c-6fe2-441c-8c8c-71466251a162
      492c30af
  15. 30 8月, 2008 1 次提交
  16. 18 11月, 2007 1 次提交