- 27 2月, 2014 13 次提交
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由 Peter Maydell 提交于
Implement the A64 view of the VBAR system register. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement the AArch64 TCR_EL1, which is the 64 bit view of the AArch32 TTBCR. (The uses of the bits in the register are completely different, but in any given situation the CPU will always interpret them one way or the other. In fact for QEMU EL1 is always 64 bit, but we share the state field because this is the correct mapping to permit a future implementation of EL2.) We also make the AArch64 view the 'master' as far as migration and reset is concerned. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement the AArch64 view of the system control register SCTLR_EL1. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement the AArch64 memory attribute registers. Since QEMU doesn't model caches it does not need to care about memory attributes at all, and we can simply make these read-as-written. We did not previously implement the AArch32 versions of the MAIR registers, which went unnoticed because of the overbroad TLB_LOCKDOWN reginfo definition; provide them now to keep the 64<->32 register relationship clear. We already provided AMAIR registers for 32 bit as simple RAZ/WI; extend that to provide a 64 bit RAZ/WI AMAIR_EL1. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
We don't support letting the guest do debug, but Linux prods the monitor debug system control register anyway, so implement a dummy RAZ/WI version. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement the AArch64 TLB invalidate operations. This is the full set of TLBI ops defined for a CPU which doesn't implement EL2 or EL3. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Implement all the AArch64 cache invalidate and clean ops (which are all NOPs since QEMU doesn't emulate the cache). The only remaining unimplemented cache op is DC ZVA. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement the AArch64 view of the MIDR system register (for AArch64 it is a simple constant, unlike the complicated mess that TI925 imposes on the 32-bit view). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement the CurrentEL sysreg. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR) visible to AArch64. These are mostly simple 64-bit extensions of the existing 32 bit system registers and so can share reginfo definitions. CTR needs to have a split definition, but we can clean up the temporary user-mode implementation in favour of using the CPU-specified reset value, and implement the system-mode-required semantics of restricting its EL0 accessibility if SCTLR.UCT is not set. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
The raw read and write functions were using the ARM_CP_64BIT flag in ri->type to determine whether to treat the register's state field as uint32_t or uint64_t; however AArch64 register info structs don't use that flag. Abstract out the "how big is the field?" test into a function and fix it to work for AArch64 registers. For this to work we must ensure that the reginfo structs put into the hashtable have the correct state field for their use, not the placeholder STATE_BOTH. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
In ARMv5 level 2 page table descriptors, each 4K or 64K page is split into four subpages, each of which can have different access permission settings, which are specified by four two-bit fields in the l2 descriptor. A long-standing cut-and-paste error meant we were using the wrong bits in the virtual address to select the access-permission field for 4K pages. The error has presumably not been noticed before because most guests don't make use of the ability to set the access permissions differently for each 1K subpage: if the guest gives the whole page the same access permissions it doesn't matter which of the 4 AP fields we select. (The whole issue is irrelevant for ARMv7 CPUs anyway because subpages aren't supported there.) Reported-by: NVivek Rai <Vivek.Rai@emulex.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1392667690-8731-1-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Correct some obviously nonsensical bit manipulation spotted by Coverity when constructing the short-form PAR value for ATS operations. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1392659525-8335-1-git-send-email-peter.maydell@linaro.org
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- 20 2月, 2014 9 次提交
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由 Peter Maydell 提交于
The write_raw_cp_reg's value argument should be a uint64_t, since that's what all its callers hand it and what all the functions it calls take. A (harmless) typo meant we were accidentally declaring it as int64_t. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
The read_raw_cp_reg and write_raw_cp_reg functions can now never fail (in fact they should never have failed previously unless there was a bug in a reginfo that meant no raw accessor was provided for a might-trap register). This allows us to clean up their prototypes so the write function returns void and the read function returns the value read, which in turn lets us simplify the callers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
All cpreg read and write functions now return 0, so we can clean up their prototypes: * write functions return void * read functions return the value rather than taking a pointer to write the value to This is a fairly mechanical change which makes only the bare minimum set of changes to the callers of read and write functions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Convert the remaining miscellaneous cases of reginfo read/write functions returning EXCP_UDEF to use an accessfn instead: TEEHBR, and the ATS address-translation operations. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the reginfo structs for the generic timer registers to use access functions rather than returning EXCP_UDEF from their read handlers. In some cases this allows us to remove a read handler completely. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Convert the performance monitor reginfo definitions to use an accessfn rather than returning EXCP_UDEF from read and write functions. This also allows us to fix a couple of XXX cases where we weren't imposing the access restrictions on RAZ/WI or constant registers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
The ARM946 has 8 PRBS (protection region base and size) registers. Currently we implement these with a CP_ANY reginfo; however this underdecodes (since there are 16 possible values of CRm but only 8 registers) and we catch the invalid values in the read and write functions. However this causes issues with migration since we only migrate the first of a wildcard register set, so we only migrate c6_region[0]. It also makes it awkward to pull reginfo access checks out into their own function. Avoid all these problems by just defining separate reginfo structs for each of the 8 registers; this also lets us avoid having any read or write functions and will result in more efficient direct field accesses from generated code. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier. In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guard the use of them in check_ap() so that we don't get incorrect results for ARMv8 CPUs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
The SCTLR is full of bits for enabling or disabling various things, and so there are many places in the code which check if certain bits are set. Define some named constants for the SCTLR bits so these checks are easier to read. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 11 2月, 2014 3 次提交
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由 Edgar E. Iglesias 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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由 Edgar E. Iglesias 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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由 Edgar E. Iglesias 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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- 31 1月, 2014 2 次提交
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由 Will Newton 提交于
This helper sets the rounding mode in the standard_fp_status word to allow NEON instructions to modify the rounding mode whilst using the standard FPSCR values for everything else. Signed-off-by: NWill Newton <will.newton@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Will Newton 提交于
This function will be needed for AArch32 ARMv8 support, so move it to helper.c where it can be used by both targets. Also moves the code out of line, but as it is quite a large function I don't believe this should be a significant performance impact. Signed-off-by: NWill Newton <will.newton@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 09 1月, 2014 11 次提交
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由 Peter Maydell 提交于
Add support for FCVT between half, single and double precision. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
This patch adds support for those instructions in the "Floating-point data-processing (1 source)" group which are simple 32-bit-to-32-bit or 64-bit-to-64-bit operations (ie everything except FCVT between single/double/half precision). We put the new round-to-int helpers in helper.c because they will also be used by the new ARMv8 A32/T32 rounding instructions. Signed-off-by: NAlexander Graf <agraf@suse.de> [WN: Commit message tweak, merged single and double precision patches, updated to new infrastructure.] Signed-off-by: NWill Newton <will.newton@linaro.org> [PMM: reworked decode, split FCVT out into their own patch] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
This patch adds emulation for the instruction group labeled "Floating-point <-> fixed-point conversions" in the ARM ARM. Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU (scalar, fixed-point). Signed-off-by: NAlexander Graf <agraf@suse.de> [WN: Commit message tweak, rebased, updated to new infrastructure. Applied bug fixes from Michael Matz and Janne Grunau.] Signed-off-by: NWill Newton <will.newton@linaro.org> [PMM: significant cleanup] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Will Newton 提交于
Define the full set of floating point to fixed point conversion helpers required to support AArch64. Signed-off-by: NWill Newton <will.newton@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
The VFP fixed point conversion helpers first call float_scalbn and then convert the result to an integer. This scalbn operation may set floating point exception flags for: * overflow & inexact (if it overflows to infinity) * input denormal squashed to zero * output denormal squashed to zero Of these, we only care about the input-denormal flag, since the output of the whole scale-and-convert operation will be an integer (so squashed-output-denormal and overflow don't apply). Suppress the others by saving the pre-scalb exception flags and only copying across a potential input-denormal flag. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Will Newton 提交于
The VFP conversion helpers for A32 round to zero as this is the only rounding mode supported. Rename these helpers to make it clear that they round to zero and are not suitable for use in the AArch64 code. Signed-off-by: NWill Newton <will.newton@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Will Newton 提交于
Make the VFP_CONV_FIX helpers a little more flexible in preparation for the A64 uses. This requires two changes: * use the correct softfloat conversion function based on itype rather than always the int32 one; this is possible now that softfloat provides int16 versions and necessary for the future conversion-to-int64 A64 variants. This also allows us to drop the awkward 'sign' macro argument. * split the 'fsz' argument which currently controls both width of the input float type and width of the output integer type into two; this will allow us to specify the A64 64-bit-int-to-single conversion function, where the two widths are different. We can also drop the (itype##_t) cast now that softfloat guarantees that all the itype##_to_float* functions take an integer argument of exactly the correct type. Signed-off-by: NWill Newton <will.newton@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Crosthwaite 提交于
There is an inline duplication of the raw_read and raw_write function bodies. Fix by just calling raw_read/raw_write instead. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: e69281b7e1462b346cb313cf0b89eedc0568125f.1388649290.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Sergey Fedorov 提交于
Use c13_context field instead of c13_fcse for CONTEXTIDR register definition. Signed-off-by: NSergey Fedorov <s.fedorov@samsung.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1387521191-15350-1-git-send-email-s.fedorov@samsung.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
When setting rounding modes we currently just hardcode the numeric values for rounding modes in a big switch statement. With AArch64 support coming, we will need to refer to these rounding modes at different places throughout the code though, so let's better give them names so we don't get confused by accident. Signed-off-by: NAlexander Graf <agraf@suse.de> [WN: Commit message tweak, use names from ARM ARM.] Signed-off-by: NWill Newton <will.newton@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
Use the VFP_BINOP macro to provide helpers for min, max, minnum and maxnum, rather than hand-rolling them. (The float64 max version is not used by A32 but will be needed for A64.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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- 08 1月, 2014 2 次提交
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由 Peter Maydell 提交于
Add support for FCVT between half, single and double precision. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
This patch adds support for those instructions in the "Floating-point data-processing (1 source)" group which are simple 32-bit-to-32-bit or 64-bit-to-64-bit operations (ie everything except FCVT between single/double/half precision). We put the new round-to-int helpers in helper.c because they will also be used by the new ARMv8 A32/T32 rounding instructions. Signed-off-by: NAlexander Graf <agraf@suse.de> [WN: Commit message tweak, merged single and double precision patches, updated to new infrastructure.] Signed-off-by: NWill Newton <will.newton@linaro.org> [PMM: reworked decode, split FCVT out into their own patch] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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