1. 24 8月, 2013 2 次提交
  2. 22 8月, 2013 2 次提交
    • A
      Merge remote-tracking branch 'luiz/queue/qmp' into staging · 5211333b
      Anthony Liguori 提交于
      # By Laszlo Ersek (8) and others
      # Via Luiz Capitulino
      * luiz/queue/qmp:
        scripts/qapi.py: Avoid syntax not supported by Python 2.4
        monitor: print the invalid char in error message
        OptsVisitor: introduce unit tests, with test cases for range flattening
        add "test-int128" and "test-bitops" to .gitignore
        OptsVisitor: don't try to flatten overlong integer ranges
        OptsVisitor: opts_type_uint64(): recognize intervals when LM_IN_PROGRESS
        OptsVisitor: rebase opts_type_uint64() to parse_uint_full()
        OptsVisitor: opts_type_int(): recognize intervals when LM_IN_PROGRESS
        OptsVisitor: introduce list modes for interval flattening
        OptsVisitor: introduce basic list modes
        Convert stderr message calling error_get_pretty() to error_report()
      
      Message-id: 1377015041-6567-1-git-send-email-lcapitulino@redhat.com
      Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>
      5211333b
    • A
      Merge remote-tracking branch 'jliu/or32' into staging · 9fe48069
      Anthony Liguori 提交于
      # By Jia Liu
      # Via Jia Liu
      * jliu/or32:
        hw/openrisc: Avoid undefined shift in openrisc_pic_cpu_handler()
        hw/openrisc: Fix masking in openrisc_pic_cpu_handler()
        hw/openrisc: Avoid using uninitialised variable 'entry'
      
      Message-id: 1377050811-11116-1-git-send-email-proljc@gmail.com
      Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>
      9fe48069
  3. 21 8月, 2013 4 次提交
    • J
      hw/openrisc: Avoid undefined shift in openrisc_pic_cpu_handler() · 7717f248
      Jia Liu 提交于
      In C99 signed shift (1 << 31) is undefined behavior, since the result
      exceeds INT_MAX.  Use 1U instead and move the shift after the check.
      Signed-off-by: NXi Wang <xi.wang@gmail.com>
      Acked-by: NJia Liu <proljc@gmail.com>
      7717f248
    • J
      hw/openrisc: Fix masking in openrisc_pic_cpu_handler() · ed396e2b
      Jia Liu 提交于
      Consider the masking of PICSR and PICMR:
      
          ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i)))
      
      To correctly mask bits, we should use the bitwise AND "&" rather than
      the logical AND "&&".  Also, the loop is not necessary for masking.
      Simply use (cpu->env.picsr & cpu->env.picmr).
      Signed-off-by: NXi Wang <xi.wang@gmail.com>
      Acked-by: NJia Liu <proljc@gmail.com>
      ed396e2b
    • J
      hw/openrisc: Avoid using uninitialised variable 'entry' · b6d9766d
      Jia Liu 提交于
      clang warns that cpu_openrisc_load_kernel() can use 'entry' uninitialized:
      
      hw/openrisc/openrisc_sim.c:69:9: error: variable 'entry' is used uninitialized
      whenever '&&' condition is false [-Werror,-Wsometimes-uninitialized]
      
          if (kernel_filename && !qtest_enabled()) {
              ^~~~~~~~~~~~~~~
      hw/openrisc/openrisc_sim.c:91:19: note: uninitialized use occurs here
          cpu->env.pc = entry;
                        ^~~~~
      
      Fix this by not attempting to change the CPU's starting PC unless
      we actually loaded a kernel.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: NJia Liu <proljc@gmail.com>
      b6d9766d
    • A
      Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20130820' into staging · ecfe10c9
      Anthony Liguori 提交于
      target-arm queue
      
      # gpg: Signature made Tue 20 Aug 2013 08:56:28 AM CDT using RSA key ID 14360CDE
      # gpg: Can't check signature: public key not found
      
      # By Peter Maydell (20) and Peter Chubb (1)
      # Via Peter Maydell
      * pmaydell/tags/pull-target-arm-20130820: (21 commits)
        hw/timer/imx_epit: Simplify and fix imx_epit implementation
        default-configs: Fix A9MP and A15MP config names
        hw/cpu/a15mpcore: Wire generic timer outputs to GIC inputs
        target-arm: Implement the generic timer
        target-arm: Support coprocessor registers which do I/O
        target-arm: Allow raw_read() and raw_write() to handle 64 bit regs
        hw/arm/pic_cpu: Remove the now-unneeded arm_pic_init_cpu()
        hw/arm/xilinx_zynq: Don't use arm_pic_init_cpu()
        hw/arm/vexpress: Don't use arm_pic_init_cpu()
        hw/arm/versatilepb: Don't use arm_pic_init_cpu()
        hw/arm/strongarm: Don't use arm_pic_init_cpu()
        hw/arm/realview: Don't use arm_pic_init_cpu()
        hw/arm/omap*: Don't use arm_pic_init_cpu()
        hw/arm/musicpal: Don't use arm_pic_init_cpu()
        hw/arm/kzm: Don't use arm_pic_init_cpu()
        hw/arm/integratorcp: Don't use arm_pic_init_cpu()
        hw/arm/highbank: Don't use arm_pic_init_cpu()
        hw/arm/exynos4210: Don't use arm_pic_init_cpu()
        hw/arm/armv7m: Don't use arm_pic_init_cpu()
        target-arm: Make IRQ and FIQ gpio lines on the CPU object
        ...
      
      Message-id: 1377007680-4934-1-git-send-email-peter.maydell@linaro.org
      Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>
      ecfe10c9
  4. 20 8月, 2013 32 次提交