Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
Acked-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>

Add missing 'static' qualifiers.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
Acked-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>

Add missing 'static' qualifiers.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>

Add missing 'static' qualifiers.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>

Fixing a simple typo, s/errno/err/, that caused
the error status from GDB semihosted system calls
to be returned incorrectly.
Signed-off-by: NMeador Inge <meadori@codesourcery.com>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>

Add more helpful debug information to the cadence UART.
Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>

If the guest uses a TLBWI instruction for upgrading permissions, we
don't need to flush the extra TLBs. This improve boot time performance
by about 10%.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Like r4k_map_address(), r4k_helper_tlbp() should use SEGMask to mask the
address.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Use the deposit op instead of and hardcoded bit field insertion. It
allows the host to emit the corresponding instruction if available.

At the same time remove the (lsb > msb) test. The MIPS64R2 instruction
set manual says "Because of the instruction format, lsb can never be
greater than msb, so there is no UNPREDICATABLE case for this
instruction."

(Bug reported as LP:1071149.)
Cc: Никита Канунников <n.kanunnikov@sbtcom.ru>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The result of a division by 0, or a division of INT_MIN by -1 in the
signed case, is unpredictable. Just replace 0 by 1 in that case so that
it doesn't trigger a floating point exception on the host.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Avoid the branches in movn/movz implementation and replace them with
movcond. Also update a wrong command.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Store conditional operations only need local temps in user mode. Fix
the code to use temp local only in user mode, this spares two memory
stores in system mode.

At the same time remove a wrong a wrong copied & pasted comment,
store operations don't have a register destination.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Load/store from helpers should be avoided as they are quite
inefficient. Rewrite unaligned loads instructions using TCG and
aligned loads. The number of actual loads operations to implement
an unaligned load instruction is reduced from up to 8 to 1.

Note: As we can't rely on shift by 32 or 64 undefined behaviour,
the code loads already shift by one constants.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

load/store microMIPS helpers are reinventing the wheel. Call do_lw,
do_ll, do_sw and do_sl instead of using a macro calling the cpu_*
load/store functions.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Only allocate t1 when needed.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Load/store operations use macros for historical reasons. Now that there
is no point in keeping them, replace them by direct calls to qemu_ld/st.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Rework *raise_exception*() functions so that they can be called from
other helpers, passing the return address as an argument.

Use do_raise_exception() function in update_fcr31() to correctly restore
the CPU state after an FPU exception.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

softfloat already has a few constants defined, use them instead of
redefining them in target-mips.

Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW and
FP_TO_INT64_OVERFLOW as even if they have the same value, they are
technically different (and defined differently in the MIPS ISA).

Remove the unused constants.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Instead of accessing the flags from the floating point control
register after updating it, read the softfloat flags.

This is just code cleanup and should not change the behaviour.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

For each FPU instruction that can trigger an FPU exception, to call
call update_fcr31() after.

Remove the manual NaN assignment in case of float to float operation, as
softfloat is already taking care of that. However for float to int
operation, the value has to be changed to the MIPS one. In the cvtpw_ps
case, the two registers have to be handled separately to guarantee
a correct final value in both registers.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Instead of clearing the softfloat exception flags before each floating
point instruction, reset them to 0 in update_fcr31() when an exception
is detected.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Use the new softfloat floatXX_muladd() functions to implement the madd,
msub, nmadd and nmsub instructions. At the same time replace the name of
the helpers by the name of the instruction, as the only reason for the
previous names was to keep the macros simple.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add a pickNaNMulAdd function for MIPS, implementing NaN propagation
rules for MIPS fused multiply-add instructions.

Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

When the CPU state after a possible retranslation is going to be handled
through code retranslation, we don't need to save the CPU state before.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

When the CPU state is restored through retranslation after an exception,
btarget should also be restored.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Commit 9c43b68d do not correctly check
for dead outputs when they need to be synced to memory in case of
half-dead operations.

Fix that by applying the same pattern than for the default case.
Tested-by: NStefan Weil <sw@weilnetz.de>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Mark helper functions that raise exceptions, but otherwise do not
change TCG register state, with TCG_CALL_NO_WG.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

As the block layer may decide to flush bottom-halfs while the machine is
still initializing (e.g. to read geometry data from the disk), our
postponed open event may be processed before the last frontend
registered with a muxed chardev.

Until the semantics of BHs have been clarified, use an expired timer to
achieve the same effect (suggested by Paolo Bonzini). This requires to
perform the alarm timer initialization earlier as otherwise timer
subsystem can be used before being ready.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>

All switch() decoding instruction have a default entry, so it is possible
to have unused enum entries. Remove conditional definitions of MIPS64
opcode enums, as it only makes the code less readable.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP testcases.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add 74kf and mips64dspr2-generic-cpu model for test.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Accumulator and DSPControl Access instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Compare-Pick instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Bit/Manipulation instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Multiply instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP GPR-Based Shift instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Arithmetic instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>