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  1. 05 2月, 2015 3 次提交
  3. 15 1月, 2015 1 次提交
  5. 23 12月, 2014 1 次提交
    • G
      target-arm: Merge EL3 CP15 register lists · 60fb1a87
      由 Greg Bellows 提交于 
      Merge of the v8_el2_cp_reginfo and el3_cp_reginfo ARMCPRegInfo lists.
Previously, some EL3 registers were restricted to the ARMv8 list under the
impression that they were not needed on ARMv7.  However, this is not the case
as the ARMv7/32-bit variants rely on the ARMv8/64-bit variants to handle
migration and reset.  For this reason they must always exist.
Signed-off-by: NGreg Bellows <greg.bellows@linaro.org>
Message-id: 1418406450-14961-1-git-send-email-greg.bellows@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      60fb1a87
  7. 11 12月, 2014 21 次提交
  9. 18 11月, 2014 1 次提交
    • P
      target-arm: handle address translations that start at level 3 · d6be29e3
      由 Peter Maydell 提交于 
      The ARMv8 address translation system defines that a page table walk
starts at a level which depends on the translation granule size
and the number of bits of virtual address that need to be resolved.
Where the translation granule is 64KB and the guest sets the
TCR.TxSZ field to between 35 and 39, it's actually possible to
start at level 3 (the final level). QEMU's implementation failed
to handle this case, and so we would set level to 2 and behave
incorrectly (including invoking the C undefined behaviour of
shifting left by a negative number). Correct the code that
determines the starting level to deal with the start-at-3 case,
by replacing the if-else ladder with an expression derived from
the ARM ARM pseudocode version.

This error was detected by the Coverity scan, which spotted
the potential shift by a negative number.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1415890569-7454-1-git-send-email-peter.maydell@linaro.org
      d6be29e3
  11. 24 10月, 2014 6 次提交
  13. 30 9月, 2014 7 次提交