- 18 4月, 2014 9 次提交
-
-
由 Rob Herring 提交于
Implement AArch64 views of ESR_EL1 and FAR_EL1, and make the 32 bit DFSR, DFAR, IFAR share state with them as architecturally specified. The IFSR doesn't share state with any AArch64 register visible at EL1, so just rename the state field without widening it to 64 bits. Signed-off-by: NRob Herring <rob.herring@linaro.org> [PMM: Minor tweaks; fix some bugs involving inconsistencies between use of offsetof() or offsetoflow32() and struct field width] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
The ARM946 model currently uses the c5_data and c5_insn fields in the CPU state struct to store the contents of its access permission registers. This is confusing and a good source of bugs because for all the MMU-based CPUs those fields are fault status and fault address registers, which behave completely differently; they just happen to use the same cpreg encoding. Split them out to use their own fields instead. These registers are only present in PMSAv5 MPU systems (of which the ARM946 is our only current example); PMSAv6 and PMSAv7 (which we have no implementations of) handle access permissions differently. We name the new state fields accordingly. Note that this change fixes a bug where a data abort or prefetch abort on the ARM946 would accidentally corrupt the access permission registers because the interrupt handling code assumed the c5_data and c5_insn fields were always fault status registers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Implement the DC ZVA instruction, which clears a block of memory. The fast path obtains a pointer to the underlying RAM via the TCG TLB data structure so we can do a direct memset(), with fallback to a simple byte-store loop in the slow path. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Suppress the ID_AA64DFR0_EL1 PMUVer field, even if the CPU specific value claims that it exists. QEMU doesn't currently implement it, and not advertising it prevents the guest from trying to use it and getting UNDEFs on unimplemented registers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> --- This is arguably a hack, but otherwise Linux tries to prod half a dozen PMU sysregs.
-
由 Rob Herring 提交于
Add support for v8 page table walks. This supports stage 1 translations for 4KB, 16KB and 64KB page sizes starting with 0 or 1 level. Signed-off-by: NRob Herring <rob.herring@linaro.org> [PMM: fix style nits, fold in 16/64K page support patch, use arm_el_is_aa64() to decide whether to do 64 bit page table walk] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Rob Herring 提交于
Set up the required syndrome information when we detect an MMU fault. Signed-off-by: NRob Herring <rob.herring@linaro.org> [PMM: split out from exception handling patch, tweaked to bring in line with how we create other kinds of syndrome information] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
For AArch32 exceptions, the only information provided about the cause of an exception is the individual exception type (data abort, undef, etc), which we store in cs->exception_index. For AArch64, the CPU provides much more detail about the cause of the exception, which can be found in the syndrome register. Create a set of fields in CPUARMState which must be filled in whenever an exception is raised, so that exception entry can correctly fill in the syndrome register for the guest. This includes the information which in AArch32 appears in the DFAR and IFAR (fault address registers) and the DFSR and IFSR (fault status registers) for data aborts and prefetch aborts, since if we end up taking the MMU fault to AArch64 rather than AArch32 this will need to end up in different system registers. This patch does a refactoring which moves the setting of the AArch32 DFAR/DFSR/IFAR/IFSR from the point where the exception is raised to the point where it is taken. (This is no change for cores with an MMU, retains the existing clearly incorrect behaviour for ARM946 of trashing the MP access permissions registers which share the c5_data and c5_insn state fields, and has no effect for v7M because we don't implement its MPU fault status or address registers.) As a side effect of the cleanup we fix a bug in the AArch64 linux-user mode code where we were passing a 64 bit fault address through the 32 bit c6_data/c6_insn fields: it now goes via the always-64-bit exception.vaddress. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Implement the DAIF system register which is a view of the DAIF bits in PSTATE. To avoid needing a readfn, we widen the daif field in CPUARMState to uint64_t. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Currently cpu.h defines a mixture of functions and types needed by the rest of QEMU and those needed only by files within target-arm/. Split the latter out into a new header so they aren't needlessly exposed further than required. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
- 18 3月, 2014 3 次提交
-
-
由 Alex Bennée 提交于
This adds support for [UF]RSQRTE instructions. It utilises the existing NEON helpers with some changes. The changes include an explicit passing of fpstatus (so the correct one is used between arm32 and aarch64), denormilzation, more correct error handling and also proper scaling of the fraction going into the estimate. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-25-git-send-email-peter.maydell@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Alex Bennée 提交于
Implement URECPE and FRECPE instructions in both scalar and vector forms. The actual reciprocal estimate function is shared with the A32/T32 Neon code. However in A64 we aren't using the Neon "standard FPSCR value" so extra checks are necessary to handle non-squashed denormal inputs which can never happen for A32/T32. Calling conventions for the helpers are thus modified to pass the fpst directly; we mark the helpers as TCG_CALL_NO_RWG since we're changing the declarations anyway. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-21-git-send-email-peter.maydell@linaro.org
-
由 Peter Maydell 提交于
Now that the PMCR writefn makes timer accesses, its reginfo needs the ARM_CP_IO flag, so that icount mode works correctly. (Fixes the bug accidentally introduced in commit 7c2cb42b). Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1394908291-16546-1-git-send-email-peter.maydell@linaro.org
-
- 15 3月, 2014 1 次提交
-
-
由 Stefan Weil 提交于
Codespell found and fixed these new typos: * doesnt -> doesn't * funtion -> function * perfomance -> performance * remaing -> remaining A coding style issue (line too long) was fixed manually. Signed-off-by: NStefan Weil <sw@weilnetz.de> Reviewed-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
-
- 14 3月, 2014 8 次提交
-
-
由 Andreas Färber 提交于
Signed-off-by: NAndreas Färber <afaerber@suse.de>
-
由 Andreas Färber 提交于
Signed-off-by: NAndreas Färber <afaerber@suse.de>
-
由 Andreas Färber 提交于
Signed-off-by: NAndreas Färber <afaerber@suse.de>
-
由 Andreas Färber 提交于
Signed-off-by: NAndreas Färber <afaerber@suse.de>
-
由 Andreas Färber 提交于
Signed-off-by: NAndreas Färber <afaerber@suse.de>
-
由 Andreas Färber 提交于
Note that while such functions may exist both for *-user and softmmu, only *-user uses the CPUState hook, while softmmu reuses the prototype for calling it directly. Signed-off-by: NAndreas Färber <afaerber@suse.de>
-
由 Andreas Färber 提交于
All targets using it gain the ability to set -cpu name,key=value,... options via the default TYPE_CPU CPUClass::parse_features() implementation. Signed-off-by: NAndreas Färber <afaerber@suse.de>
-
由 Andreas Färber 提交于
Commits ab1da857, fdfba1a2, 2c17449b added usages of ENV_GET_CPU() macro to target-specific code. Use arm_env_get_cpu() instead and enforce separating variable declarations. Cc: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: NAndreas Färber <afaerber@suse.de>
-
- 10 3月, 2014 2 次提交
-
-
由 Alistair Francis 提交于
This patch implements the ARM PMCCNTR register including the disable and reset components of the PMCR register. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: bbf405e1feaf352cf39d5db402c9efcbd0f57c78.1393459802.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Peter Maydell 提交于
Commit 4cc35614 moved the exception mask bits out of env->uncached_cpsr and into env->daif. However the env->daif contents are AArch64 style mask bits, which include not just the AArch32 AIF bits but also the new D bit (masks debug exceptions). This means that when reconstructing the AArch32 CPSR value we must not allow the D bit in env->daif to get into the CPSR, because the corresponding bit in the CPSR is E, the endianness bit. This bug didn't affect execution under TCG because we don't implement endianness-swapping and so simply ignored the E bit; however it meant that kernel booting under KVM failed, because KVM does honour the E bit. Reported-by: NAlexey Ignatov <lexszero@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
- 27 2月, 2014 17 次提交
-
-
由 Will Newton 提交于
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8 and add a CPU feature flag to enable these instructions. The CRC32-C implementation used is the built-in qemu implementation and The CRC-32 implementation is from zlib. This requires adding zlib to LIBS to ensure it is linked for the linux-user binary. Signed-off-by: NWill Newton <will.newton@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1393411566-24104-3-git-send-email-will.newton@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Peter Maydell 提交于
Implement the AArch64 view of the CPACR. The AArch64 CPACR is defined to have a lot of RES0 bits, but since the architecture defines that RES0 bits may be implemented as reads-as-written and we know that a v8 CPU will have no registered coprocessors for cp0..cp13 we can safely implement the whole register this way. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
To avoid complication in code that otherwise would not need to care about whether EL1 is AArch32 or AArch64, we should store the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF in AArch64) in one place consistently regardless of EL1's mode. Since AArch64 has an extra enable bit (D for debug exceptions) which isn't visible in AArch32, this means we need to keep the enables in env->pstate. (This is also consistent with the general approach we're taking that we handle 32 bit CPUs as being like AArch64/ARMv8 CPUs but which only run in 32 bit mode.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Define a dummy version of the AArch64 OSLAR_EL1 system register which just ignores writes. Linux will always write to this (it is the OS lock used for debugging), but we don't support debug. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
In AArch64 the breakpoint and watchpoint registers are mandatory, so the kernel always accesses them on bootup. Implement dummy versions, which read as written but have no actual effect. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Implement the AArch64-specific ID and feature registers. Although many of these are currently not used by the architecture (and so always zero for all implementations), we define the full set of fields in the ARMCPU struct for symmetry. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Implement the AArch64 view of the generic timer system registers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Peter Maydell 提交于
Implement the AArch64 MPIDR system register. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Implement the AArch64 TTBR* registers. For v7 these were already 64 bits to handle LPAE, but implemented as two separate uint32_t fields. Combine them into a single uint64_t which can be used for all purposes. Since this requires touching every use, take the opportunity to rename the field to the architectural name. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Implement the A64 view of the VBAR system register. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Implement the AArch64 TCR_EL1, which is the 64 bit view of the AArch32 TTBCR. (The uses of the bits in the register are completely different, but in any given situation the CPU will always interpret them one way or the other. In fact for QEMU EL1 is always 64 bit, but we share the state field because this is the correct mapping to permit a future implementation of EL2.) We also make the AArch64 view the 'master' as far as migration and reset is concerned. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Implement the AArch64 view of the system control register SCTLR_EL1. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Implement the AArch64 memory attribute registers. Since QEMU doesn't model caches it does not need to care about memory attributes at all, and we can simply make these read-as-written. We did not previously implement the AArch32 versions of the MAIR registers, which went unnoticed because of the overbroad TLB_LOCKDOWN reginfo definition; provide them now to keep the 64<->32 register relationship clear. We already provided AMAIR registers for 32 bit as simple RAZ/WI; extend that to provide a 64 bit RAZ/WI AMAIR_EL1. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
We don't support letting the guest do debug, but Linux prods the monitor debug system control register anyway, so implement a dummy RAZ/WI version. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Implement the AArch64 TLB invalidate operations. This is the full set of TLBI ops defined for a CPU which doesn't implement EL2 or EL3. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
-
由 Peter Maydell 提交于
Implement all the AArch64 cache invalidate and clean ops (which are all NOPs since QEMU doesn't emulate the cache). The only remaining unimplemented cache op is DC ZVA. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-
由 Peter Maydell 提交于
Implement the AArch64 view of the MIDR system register (for AArch64 it is a simple constant, unlike the complicated mess that TI925 imposes on the 32-bit view). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
-