We need a possibility to run code when a subchannel gets disabled.
This patch adds the necessary infrastructure.
Signed-off-by: NThomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: NCornelia Huck <cornelia.huck@de.ibm.com>
Reviewed-by: NMichael S. Tsirkin <mst@redhat.com>

Update for "s390-ccw.img: Consume service interrupts".
Signed-off-by: NCornelia Huck <cornelia.huck@de.ibm.com>

We have to consume the outstanding service interrupt after each
service call, otherwise a correct implementation will return
CC=2 on subsequent service calls.
Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com>
Reviewed-by: NDavid Hildenbrand <dahi@linux.vnet.ibm.com>
Signed-off-by: NCornelia Huck <cornelia.huck@de.ibm.com>

Our main channel_subsys structure is not a device (yet), but we need
to setup mss/mcss-e again if the guest had enabled it before. Use
a hack that should catch most configurations (assuming that the guest
will have enabled at least one device in higher subchannel sets or
channel subsystems if it enabled the functionality.)
Signed-off-by: NCornelia Huck <cornelia.huck@de.ibm.com>

For a guest-initiated reset, we need to not only reset the virtio device,
but also reset the VirtioCcwDevice into a clean state. This includes
resetting the indicators, or else a guest will not be able to e.g.
switch from classic interrupts to adapter interrupts.

Split off this routine into a new function virtio_ccw_reset_virtio()
to make the distinction between resetting the virtio-related devices
and the base subchannel device clear.

CC: qemu-stable@nongnu.org
Signed-off-by: NCornelia Huck <cornelia.huck@de.ibm.com>
Reviewed-by: NChristian Borntraeger <borntraeger@de.ibm.com>

Trivial m68k cleanup

# gpg: Signature made Mon Jun 29 16:38:40 2015 BST using DSA key ID ABF36C53
# gpg: Good signature from "Laurent Vivier <laurent@vivier.eu>"
# gpg:                 aka "Laurent Vivier <Laurent@vivier.eu>"
# gpg:                 aka "Laurent Vivier <Laurent@lvivier.info>"
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# gpg:                 aka "[jpeg image of size 3881]"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 9EC7 B78A C0AC E697 5E4B  BDE3 34A4 F6C9 ABF3 6C53

* remotes/vivier/tags/pull-m68k-20150629:
  m68k: remove useless parameter op_size from gen_lea_indexed()
  m68k: remove useless file m68k-qreg.h
  m68k: is_mem is useless
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
Reviewed-by: NThomas Huth <huth@tuxfamily.org>

Unused since:

    commit e1f3808e
    Author: pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>
    Date:   Sat May 24 22:29:16 2008 +0000

        Convert m68k target to TCG.
Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
Reviewed-by: NThomas Huth <huth@tuxfamily.org>

Remove is_mem as it is never tested anymore since:

    commit bfa50bc2
    Author: aliguori <aliguori@c046a42c-6fe2-441c-8c8c-71466251a162>
    Date:   Tue Nov 18 20:26:41 2008 +0000

        Remove premature memop TB terminations (Jan Kiszka)
Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
Reviewed-by: NThomas Huth <huth@tuxfamily.org>

TriCore bugfixes

# gpg: Signature made Mon Jun 29 13:08:17 2015 BST using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>"

* remotes/bkoppelmann/tags/pull-tricore-20150629:
  target-tricore: fix depositing bits from PCXI into ICR
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Spotted by Coverity, because (env->PCXI & MASK_PCXI_PCPN) >> 24
is always zero.  The immediately preceding assignment is also
wrong though.
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1435147270-1040-1-git-send-email-pbonzini@redhat.com>

virtio, pci fixes, enhancements

Almost exclusively bugfixes, though in this case,
we are adding functionality to the pxb in order
to make OVMF work on it.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Fri Jun 26 14:43:27 2015 BST using RSA key ID D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"

* remotes/mst/tags/for_upstream:
  Fix glib_subprocess test
  hw/pci-bridge: format special OFW unit address for PXB host
  hw/core: explicit OFW unit address callback for SysBusDeviceClass
  hw/pci-bridge: disable SHPC in PXB
  hw/pci-bridge: introduce "shpc" property
  hw/pci: introduce shpc_present() helper function
  hw/pci-bridge: add macro for "msi" property
  hw/pci-bridge: add macro for "chassis_nr" property
  hw/pci-bridge: expose _test parameter in SHPC_VMSTATE()
  migration: introduce VMSTATE_BUFFER_UNSAFE_INFO_TEST()
  add pci-bridge-seat
  pc: cleanup and convert TMP ACPI device description to AML API
  MAINTAINERS: add ACPI entry
  vhost: correctly pass error to caller in vhost_dev_enable_notifiers()
  balloon: add a feature bit to let Guest OS deflate balloon on oom
  qdev: fix OVERFLOW_BEFORE_WIDEN
  virito-pci: fix OVERRUN problem
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

target-arm queue:
 * Change the virt board's default interface type for block devices to virtio
 * Improve some error messages that will now be triggered by some incorrect
   but previously worked-by-accident command lines
 * Print ELR if we're doing debug logging of AArch64 exception entry
 * Handle the "completely empty semihosting commandline" correctly for
   softmmu (we already did for linux-user)
 * Add GICv2m description to ACPI tables for virt board
 * Fix some incorrect table revision entries in virt board ACPI tables

# gpg: Signature made Fri Jun 26 14:29:39 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20150626:
  hw/arm/virt: Make block devices default to virtio
  qdev-properties-system: Improve error message for drive assignment conflict
  qdev-properties-system: Change set_pointer's parse callback to use Error
  target-arm: A64: Print ELR when taking exceptions
  target-arm: default empty semihosting cmdline
  hw/arm/virt-acpi-build: Add GICv2m description in ACPI MADT table
  hw/arm/virt-acpi-build: Fix table revision and some comments
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Now we have virtio-pci, we can make the virt board's default block
device type be IF_VIRTIO. This allows users to use simplified
command lines that don't have to explicitly create virtio-pci-blk
devices; the -hda &c very short options now also work.

This means we also need to set no_cdrom to avoid getting a
default cdrom device -- this is needed because the virtio-blk
device will fail if it is connected to a block backend with
no media, which is what the default cdrom device typically is.
Providing a cdrom with media via -cdrom will succeed, but silently
create a device with non-removable medium. this is probably
not really what the user wants, but is the best we can do now.

Note that this change means that some command lines which used
to work (by accident) will stop working. Where a drive was connected
manually to a device but without 'if=none' being specified, we
used to treat this as an IDE drive, which we would then not autoplug
because the board doesn't support IDE. Now we will treat it as a
virtio disk and autoplug it, which means the attempt to use the
drive manually will fail:
  qemu-system-arm: -drive file=img.qcow2,id=foo: Drive 'foo' is already
  in use because it has been automatically connected to another device
  (did you need 'if=none' in the drive options?)
The command line will have to be changed to include 'if=none', as the
error message suggests.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
Reviewed-by: NStefan Hajnoczi <stefanha@redhat.com>
Message-id: 1435068107-12594-4-git-send-email-peter.maydell@linaro.org

If the user forgot if=none on their drive specification they're likely
to get an error message because the drive is assigned once automatically
by QEMU and once by the manual id=/drive= user command line specification.
Improve the error message produced in this case to explicitly guide the
user towards if=none.

We rephrase the "drive conflict but not for an if=something" error as
well to keep the wording in line.

The two cases that change are:

(1) Drive specified as to be auto-connected and also manually connected
(and the board does handle this if= type):

  qemu-system-x86_64 -nodefaults -display none \
     -drive if=scsi,file=tmp.qcow2,id=foo -device ide-hd,drive=foo

Previously:
  qemu-system-x86_64: -device ide-hd,drive=foo: Property 'ide-hd.drive'
  can't take value 'foo', it's in use

Now:
  qemu-system-x86_64: -device ide-hd,drive=foo: Drive 'foo' is already in
  use because it has been automatically connected to another device (did
  you need 'if=none' in the drive options?)

(2) Drive specified to be manually connected in two different ways:

  qemu-system-x86_64 -nodefaults -display none \
   -drive if=none,file=tmp.qcow2,id=foo -device ide-hd,drive=foo \
   -device ide-hd,drive=foo

Previously:
  qemu-system-x86_64: -device ide-hd,drive=foo: Property 'ide-hd.drive'
  can't take value 'foo', it's in use

Now:
  qemu-system-x86_64: -device ide-hd,drive=foo: Drive 'foo' is already in
  use by another device
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
Reviewed-by: NStefan Hajnoczi <stefanha@redhat.com>
Message-id: 1435068107-12594-3-git-send-email-peter.maydell@linaro.org

Instead of having set_pointer() call a parse callback which returns
an error number that we then convert to an Error string with
error_set_from_qdev_prop_error(), make the parse callback take an
Error** and set the error itself. This will allow parse routines
to provide more helpful error messages than the generic ones.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
Reviewed-by: NStefan Hajnoczi <stefanha@redhat.com>
Message-id: 1435068107-12594-2-git-send-email-peter.maydell@linaro.org

When taking an exception print the content of the exception link
register. This is useful especially for synchronous exceptions because
in that case this registers holds the address of the instruction that
generated the exception.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Message-id: 1435036655-16132-1-git-send-email-soren.brinkmann@xilinx.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

If neither explicit semihosting args nor -kernel are used,
make SYS_GET_CMDLINE return an empty string.
Signed-off-by: NLiviu Ionescu <ilg@livius.net>
Message-id: AC7B5AFC-06AE-4FAD-9852-B65708E80E09@livius.net
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add GICv2m description in ACPI MADT table, so guest can use MSI when
booting with ACPI.
Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: NAndrew Jones <drjones@redhat.com>
Tested-by: NAndrew Jones <drjones@redhat.com>
Message-id: 1434676210-2276-1-git-send-email-shannon.zhao@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

The table revision is not the ACPI spec version. Fix the wrong revision
and also some comments.
Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: NMichael S. Tsirkin <mst@redhat.com>
Message-id: 1433820378-8336-1-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

MIPS patches 2015-06-26

Changes:
* MIPS UHI semihosting support
* microMIPS32 R6 support

# gpg: Signature made Fri Jun 26 10:42:33 2015 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20150626:
  target-mips: add mips32r6-generic CPU definition
  target-mips: microMIPS32 R6 POOL16{A, C} instructions
  target-mips: microMIPS32 R6 Major instructions
  target-mips: microMIPS32 R6 POOL32{I, C} instructions
  target-mips: microMIPS32 R6 POOL32F instructions
  target-mips: microMIPS32 R6 POOL32A{XF} instructions
  target-mips: microMIPS32 R6 branches and jumps
  target-mips: add microMIPS32 R6 opcode enum
  target-mips: signal RI for removed instructions in microMIPS R6
  target-mips: raise RI exceptions when FIR.PS = 0
  target-mips: rearrange gen_compute_compact_branch
  target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP
  target-mips: remove an unused argument
  target-mips: add microMIPS TLBINV, TLBINVF
  target-mips: fix {RD, WR}PGPR in microMIPS
  target-mips: convert host to MIPS errno values when required
  target-mips: add Unified Hosting Interface (UHI) support
  target-mips: remove identical code in different branch
  hw/mips: Do not clear BEV for MIPS malta kernel load
  include/softmmu-semi.h: Make semihosting support 64-bit clean
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Define a new CPU definition supporting MIPS32 Release 6 ISA and
microMIPS32 Release 6 ISA.
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

microMIPS32 Release 6 POOL16A/ POOL16C instructions
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

Add new microMIPS32 Release 6 Major opcode instructions
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

Add new microMIPS32 Release 6 POOL32I/POOL32C type instructions
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

Add new microMIPS32 Release 6 POOL32F instructions
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

Add new microMIPS32 Release 6 pool32a/pool32axf instructions.
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

Add new microMIPS32 Release 6 branch and jump instructions.
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

Add microMIPS32 Release 6 opcode enum.
Remove RI checking for pre-R6 reserved opcode.
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

Signal a Reserved Instruction exception for removed instruction encoding
in microMIPS Release 6.
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

64-bit paired-single (PS) floating point data type is optional in the
pre-Release 6.
It has to raise RI exception when PS type is not implemented. (FIR.PS = 0)
(The PS data type is removed in the Release 6.)
Loongson-2E and Loongson-2F don't have any implementation field in
FCSR0(FIR) but do support PS data format, therefore for these cores RI will
not be signalled regardless of PS bit.
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

The function will be also used for microMIPS Release 6.
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

Refactor those instructions in order to reuse them for microMIPS32
Release 6.
Rearrange gen_move_low32().
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

Remove an unused argument from decode_micromips32_opc()
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

Add microMIPS TLBINV, TLBINVF
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

rt, rs were swapped
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>

Convert only errno values which can be returned by system calls in
mips-semi.c and are not generic to all archs.
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>

Add UHI semihosting support for MIPS. QEMU run with "-semihosting" option
will alter the behaviour of SDBBP 1 instruction -- UHI operation will be
called instead of generating a debug exception.

Also tweak Malta's pseudo-bootloader. On CPU reset the $4 register is set
to -1 if semihosting arguments are passed to indicate that the UHI
operations should be used to obtain input arguments.
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>

The BEV flag controls whether the boot exception vector is still
in place when starting a kernel.  When cleared the exception vector
at EBASE (or hard coded address of 0x80000000) is used instead.

The early stages of the linux kernel would benefit from BEV still
being set to ensure any faults get handled by the boot rom exception
handlers.  This is a moot point for system qemu as there aren't really
any BEV handlers, but there are other good reasons to change this...

The UHI (semi-hosting interface) defines special behaviours depending
on whether an application starts in an environment with BEV set or
cleared. When BEV is set then UHI assumes that a bootloader is
relatively dumb and has no advanced exception handling logic.
However, when BEV is cleared then UHI assumes that the bootloader
has the ability to handle UHI exceptions with its exception handlers
and will unwind and forward UHI SYSCALL exceptions to the exception
vector that was installed prior to running the application.
Signed-off-by: NMatthew Fortune <matthew.fortune@imgtec.com>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>