- 06 10月, 2009 1 次提交
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由 Juan Quintela 提交于
There was a missmerge, and then we got a tail recursive call to cpu_post_load without case base :) Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 05 10月, 2009 21 次提交
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由 Jan Kiszka 提交于
Commit 56aebc89 changed gdbstub in way that debugging 32 or 16-bit guest code is no longer possible with qemu for x86_64 guest CPUs. Since that commit, qemu only provides registers sets for 64-bit, forcing current and foreseeable gdb to also switch its architecture to 64-bit. And this breaks if the inferior is 32 or 16 bit. No question, this is a gdb issue. But, as it was confirmed in several discusssions with gdb people, it is a non-trivial thing to fix. So until qemu finds a gdb version attach with a rework x86 support, we have to work around it by switching the register layout as the guest switches its execution mode between 16/32 and 64 bit. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
mce_banks is always MCE_BANKS_DEF * 4 in size, value never change CC: Huang Ying <ying.huang@intel.com> Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Don't even ask, being able to load/save between 64<->80bit floats should be forbidden Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
It is needed to save the interrupt_bitmap Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
It is needed to store fptags Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
We save more that fpus on that 16 bits (fpstt), we need an additional field Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
This makes the savevm code correct, and sign extensins gives us exactly what we need (namely, sign extend to 64 bits when used with 64bit addresess. Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax. Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Kevin Wolf 提交于
This patch corrects the following aspects of exception generation in fxsave/fxrstor: * Generate #GP if the operand is not aligned to a 16 byte boundary * Generate #UD if the LOCK prefix is used * For CR0.EM = 1 #NM is generated, not #UD Signed-off-by: NKevin Wolf <mail@kevin-wolf.de> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 04 10月, 2009 3 次提交
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由 Andre Przywara 提交于
RDTSCP reads the time stamp counter and atomically also the content of a 32-bit MSR, which can be freely set by the OS. This allows CPU local data to be queried by userspace. Linux uses this to allow a fast implementation of the getcpu() syscall, which uses the vsyscall page to avoid a context switch. AMD CPUs since K8RevF and Intel CPUs since Nehalem support this instruction. RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]). Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Andre Przywara 提交于
This adds support for the AMD Phenom/Barcelona's SSE4a instructions. Those include insertq and extrq, which are doing shift and mask on XMM registers, in two versions (immediate shift/length values and stored in another XMM register). Additionally it implements movntss, movntsd, which are scalar non-temporal stores (avoiding cache trashing). These are implemented as normal stores, though. SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]). Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Andre Przywara 提交于
AMD CPUs featuring a shortcut to access CR8 even from 32-bit mode. If you use the LOCK prefix with "mov CR0", it accesses CR8 instead. This behavior is guarded by the CR8_LEGACY CPUID bit (Fn8000_0001:ECX[1]). Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 02 10月, 2009 2 次提交
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由 Anthony Liguori 提交于
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 malc 提交于
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: Nmalc <av1474@comtv.ru>
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- 01 10月, 2009 1 次提交
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由 Laurent Desnogues 提交于
Use globals for the 8 or 16 CPU registers on i386 and x86_64. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 27 9月, 2009 2 次提交
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由 Aurelien Jarno 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 26 9月, 2009 1 次提交
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由 Juan Quintela 提交于
Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 21 9月, 2009 1 次提交
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由 Blue Swirl 提交于
The CPU state parameter is not used, remove it and adjust callers. Now we can compile ioport.c once for all targets. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 12 9月, 2009 4 次提交
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由 Jan Kiszka 提交于
cpu_synchronize_state already does this. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Blue Swirl 提交于
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Blue Swirl 提交于
Problem: Our file sys-queue.h is a copy of the BSD file, but there are some additions and it's not entirely compatible. Because of that, there have been conflicts with system headers on BSD systems. Some hacks have been introduced in the commits 15cc9235, f40d7537, 96555a96 and 3990d09a but the fixes were fragile. Solution: Avoid the conflict entirely by renaming the functions and the file. Revert the previous hacks. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Gleb Natapov 提交于
Direct call to kvm_arch_get_registers() bypass logic in cpu_synchronize_state() Signed-off-by: NGleb Natapov <gleb@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 05 9月, 2009 1 次提交
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由 Blue Swirl 提交于
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 28 8月, 2009 3 次提交
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由 Avi Kivity 提交于
cpu_synchronize_state() is a little unreadable since the 'modified' argument isn't self-explanatory. Simplify it by making it always synchronize the kernel state into qemu, and automatically flush the registers back to the kernel if they've been synchronized on this exit. Signed-off-by: NAvi Kivity <avi@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Andre Przywara 提交于
In addition to the TCG based qemu64 type let's introduce a kvm64 CPU type, which is the least common denominator of all KVM-capable x86-CPUs (based on Intel Pentium 4 Prescott). It can be used as a base type for migration. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Andre Przywara 提交于
The CPUID level determines how many CPUID leafs are exposed to the guest. Some features (like multi-core) cannot be propagated without the proper level, but guests maybe confused by bogus entries in some leafs. So add level= and xlevel= to the list of -cpu options to allow the user to override the default settings. While at it, merge unnecessary local variables into one and allow hexadecimal arguments. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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