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体验新版 GitCode,发现更多精彩内容 >>
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f0fb8b71
编写于
8月 29, 2011
作者:
E
Edgar E. Iglesias
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'omap-for-upstream' of
git://git.linaro.org/people/pmaydell/qemu-arm
into pm
上级
9f4bd6ba
d5c8cf99
变更
8
展开全部
隐藏空白更改
内联
并排
Showing
8 changed file
with
733 addition
and
203 deletion
+733
-203
hw/flash.h
hw/flash.h
+1
-6
hw/nseries.c
hw/nseries.c
+18
-11
hw/omap.h
hw/omap.h
+9
-5
hw/omap2.c
hw/omap2.c
+2
-1
hw/omap_gpmc.c
hw/omap_gpmc.c
+578
-135
hw/onenand.c
hw/onenand.c
+119
-45
hw/sysbus.c
hw/sysbus.c
+5
-0
hw/sysbus.h
hw/sysbus.h
+1
-0
未找到文件。
hw/flash.h
浏览文件 @
f0fb8b71
...
...
@@ -36,12 +36,7 @@ uint32_t nand_getbuswidth(DeviceState *dev);
#define NAND_MFR_MICRON 0x2c
/* onenand.c */
void
onenand_base_update
(
void
*
opaque
,
target_phys_addr_t
new
);
void
onenand_base_unmap
(
void
*
opaque
);
void
*
onenand_init
(
BlockDriverState
*
bdrv
,
uint16_t
man_id
,
uint16_t
dev_id
,
uint16_t
ver_id
,
int
regshift
,
qemu_irq
irq
);
void
*
onenand_raw_otp
(
void
*
opaque
);
void
*
onenand_raw_otp
(
DeviceState
*
onenand_device
);
/* ecc.c */
typedef
struct
{
...
...
hw/nseries.c
浏览文件 @
f0fb8b71
...
...
@@ -33,6 +33,7 @@
#include "loader.h"
#include "blockdev.h"
#include "tusb6010.h"
#include "sysbus.h"
/* Nokia N8x0 support */
struct
n800_s
{
...
...
@@ -52,7 +53,7 @@ struct n800_s {
TUSBState
*
usb
;
void
*
retu
;
void
*
tahvo
;
void
*
nand
;
DeviceState
*
nand
;
};
/* GPIO pins */
...
...
@@ -167,13 +168,21 @@ static void n8x0_nand_setup(struct n800_s *s)
char
*
otp_region
;
DriveInfo
*
dinfo
;
dinfo
=
drive_get
(
IF_MTD
,
0
,
0
);
s
->
nand
=
qdev_create
(
NULL
,
"onenand"
);
qdev_prop_set_uint16
(
s
->
nand
,
"manufacturer_id"
,
NAND_MFR_SAMSUNG
);
/* Either 0x40 or 0x48 are OK for the device ID */
s
->
nand
=
onenand_init
(
dinfo
?
dinfo
->
bdrv
:
0
,
NAND_MFR_SAMSUNG
,
0x48
,
0
,
1
,
qdev_get_gpio_in
(
s
->
cpu
->
gpio
,
N8X0_ONENAND_GPIO
));
omap_gpmc_attach
(
s
->
cpu
->
gpmc
,
N8X0_ONENAND_CS
,
0
,
onenand_base_update
,
onenand_base_unmap
,
s
->
nand
);
qdev_prop_set_uint16
(
s
->
nand
,
"device_id"
,
0x48
);
qdev_prop_set_uint16
(
s
->
nand
,
"version_id"
,
0
);
qdev_prop_set_int32
(
s
->
nand
,
"shift"
,
1
);
dinfo
=
drive_get
(
IF_MTD
,
0
,
0
);
if
(
dinfo
&&
dinfo
->
bdrv
)
{
qdev_prop_set_drive_nofail
(
s
->
nand
,
"drive"
,
dinfo
->
bdrv
);
}
qdev_init_nofail
(
s
->
nand
);
sysbus_connect_irq
(
sysbus_from_qdev
(
s
->
nand
),
0
,
qdev_get_gpio_in
(
s
->
cpu
->
gpio
,
N8X0_ONENAND_GPIO
));
omap_gpmc_attach
(
s
->
cpu
->
gpmc
,
N8X0_ONENAND_CS
,
sysbus_mmio_get_region
(
sysbus_from_qdev
(
s
->
nand
),
0
));
otp_region
=
onenand_raw_otp
(
s
->
nand
);
memcpy
(
otp_region
+
0x000
,
n8x0_cal_wlan_mac
,
sizeof
(
n8x0_cal_wlan_mac
));
...
...
@@ -770,10 +779,8 @@ static void n8x0_usb_setup(struct n800_s *s)
TUSBState
*
tusb
=
tusb6010_init
(
tusb_irq
);
/* Using the NOR interface */
omap_gpmc_attach
(
s
->
cpu
->
gpmc
,
N8X0_USB_ASYNC_CS
,
tusb6010_async_io
(
tusb
),
NULL
,
NULL
,
tusb
);
omap_gpmc_attach
(
s
->
cpu
->
gpmc
,
N8X0_USB_SYNC_CS
,
tusb6010_sync_io
(
tusb
),
NULL
,
NULL
,
tusb
);
omap_gpmc_attach
(
s
->
cpu
->
gpmc
,
N8X0_USB_ASYNC_CS
,
tusb6010_async_io
(
tusb
));
omap_gpmc_attach
(
s
->
cpu
->
gpmc
,
N8X0_USB_SYNC_CS
,
tusb6010_sync_io
(
tusb
));
s
->
usb
=
tusb
;
qdev_connect_gpio_out
(
s
->
cpu
->
gpio
,
N8X0_TUSB_ENABLE_GPIO
,
tusb_pwr
);
...
...
hw/omap.h
浏览文件 @
f0fb8b71
...
...
@@ -118,11 +118,12 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
/* OMAP2 general purpose memory controller */
struct
omap_gpmc_s
;
struct
omap_gpmc_s
*
omap_gpmc_init
(
target_phys_addr_t
base
,
qemu_irq
irq
);
struct
omap_gpmc_s
*
omap_gpmc_init
(
struct
omap_mpu_state_s
*
mpu
,
target_phys_addr_t
base
,
qemu_irq
irq
,
qemu_irq
drq
);
void
omap_gpmc_reset
(
struct
omap_gpmc_s
*
s
);
void
omap_gpmc_attach
(
struct
omap_gpmc_s
*
s
,
int
cs
,
MemoryRegion
*
iomem
,
void
(
*
base_upd
)(
void
*
opaque
,
target_phys_addr_t
new
),
void
(
*
unmap
)(
void
*
opaque
),
void
*
opaque
);
void
omap_gpmc_attach
(
struct
omap_gpmc_s
*
s
,
int
cs
,
MemoryRegion
*
iomem
);
void
omap_gpmc_attach_nand
(
struct
omap_gpmc_s
*
s
,
int
cs
,
DeviceState
*
nand
);
/*
* Common IRQ numbers for level 1 interrupt handler
...
...
@@ -788,6 +789,7 @@ i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
# define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
# define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
# define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
# define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630)
# define cpu_is_omap15xx(cpu) \
(cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
...
...
@@ -799,7 +801,8 @@ i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
# define cpu_class_omap1(cpu) \
(cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
# define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
# define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
# define cpu_class_omap3(cpu) \
(cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
struct
omap_mpu_state_s
{
enum
omap_mpu_model
{
...
...
@@ -813,6 +816,7 @@ struct omap_mpu_state_s {
omap2423
,
omap2430
,
omap3430
,
omap3630
,
}
mpu_model
;
CPUState
*
env
;
...
...
hw/omap2.c
浏览文件 @
f0fb8b71
...
...
@@ -2402,7 +2402,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
sysbus_mmio_map
(
busdev
,
4
,
omap_l4_region_base
(
ta
,
5
));
s
->
sdrc
=
omap_sdrc_init
(
0x68009000
);
s
->
gpmc
=
omap_gpmc_init
(
0x6800a000
,
s
->
irq
[
0
][
OMAP_INT_24XX_GPMC_IRQ
]);
s
->
gpmc
=
omap_gpmc_init
(
s
,
0x6800a000
,
s
->
irq
[
0
][
OMAP_INT_24XX_GPMC_IRQ
],
s
->
drq
[
OMAP24XX_DMA_GPMC
]);
dinfo
=
drive_get
(
IF_SD
,
0
,
0
);
if
(
!
dinfo
)
{
...
...
hw/omap_gpmc.c
浏览文件 @
f0fb8b71
此差异已折叠。
点击以展开。
hw/onenand.c
浏览文件 @
f0fb8b71
...
...
@@ -25,6 +25,7 @@
#include "blockdev.h"
#include "memory.h"
#include "exec-memory.h"
#include "sysbus.h"
/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
#define PAGE_SHIFT 11
...
...
@@ -33,6 +34,7 @@
#define BLOCK_SHIFT (PAGE_SHIFT + 6)
typedef
struct
{
SysBusDevice
busdev
;
struct
{
uint16_t
man
;
uint16_t
dev
;
...
...
@@ -49,6 +51,7 @@ typedef struct {
uint8_t
*
current
;
MemoryRegion
ram
;
MemoryRegion
mapped_ram
;
uint8_t
current_direction
;
uint8_t
*
boot
[
2
];
uint8_t
*
data
[
2
][
2
];
MemoryRegion
iomem
;
...
...
@@ -120,27 +123,72 @@ static void onenand_mem_setup(OneNANDState *s)
1
);
}
void
onenand_base_update
(
void
*
opaque
,
target_phys_addr_t
new
)
static
void
onenand_intr_update
(
OneNANDState
*
s
)
{
OneNANDState
*
s
=
(
OneNANDState
*
)
opaque
;
s
->
base
=
new
;
memory_region_add_subregion
(
get_system_memory
(),
s
->
base
,
&
s
->
container
);
qemu_set_irq
(
s
->
intr
,
((
s
->
intstatus
>>
15
)
^
(
~
s
->
config
[
0
]
>>
6
))
&
1
);
}
void
onenand_base_unmap
(
void
*
opaque
)
static
void
onenand_pre_save
(
void
*
opaque
)
{
OneNANDState
*
s
=
(
OneNANDState
*
)
opaque
;
memory_region_del_subregion
(
get_system_memory
(),
&
s
->
container
);
OneNANDState
*
s
=
opaque
;
if
(
s
->
current
==
s
->
otp
)
{
s
->
current_direction
=
1
;
}
else
if
(
s
->
current
==
s
->
image
)
{
s
->
current_direction
=
2
;
}
else
{
s
->
current_direction
=
0
;
}
}
static
void
onenand_intr_update
(
OneNANDState
*
s
)
static
int
onenand_post_load
(
void
*
opaque
,
int
version_id
)
{
qemu_set_irq
(
s
->
intr
,
((
s
->
intstatus
>>
15
)
^
(
~
s
->
config
[
0
]
>>
6
))
&
1
);
OneNANDState
*
s
=
opaque
;
switch
(
s
->
current_direction
)
{
case
0
:
break
;
case
1
:
s
->
current
=
s
->
otp
;
break
;
case
2
:
s
->
current
=
s
->
image
;
break
;
default:
return
-
1
;
}
onenand_intr_update
(
s
);
return
0
;
}
static
const
VMStateDescription
vmstate_onenand
=
{
.
name
=
"onenand"
,
.
version_id
=
1
,
.
minimum_version_id
=
1
,
.
minimum_version_id_old
=
1
,
.
pre_save
=
onenand_pre_save
,
.
post_load
=
onenand_post_load
,
.
fields
=
(
VMStateField
[])
{
VMSTATE_UINT8
(
current_direction
,
OneNANDState
),
VMSTATE_INT32
(
cycle
,
OneNANDState
),
VMSTATE_INT32
(
otpmode
,
OneNANDState
),
VMSTATE_UINT16_ARRAY
(
addr
,
OneNANDState
,
8
),
VMSTATE_UINT16_ARRAY
(
unladdr
,
OneNANDState
,
8
),
VMSTATE_INT32
(
bufaddr
,
OneNANDState
),
VMSTATE_INT32
(
count
,
OneNANDState
),
VMSTATE_UINT16
(
command
,
OneNANDState
),
VMSTATE_UINT16_ARRAY
(
config
,
OneNANDState
,
2
),
VMSTATE_UINT16
(
status
,
OneNANDState
),
VMSTATE_UINT16
(
intstatus
,
OneNANDState
),
VMSTATE_UINT16
(
wpstatus
,
OneNANDState
),
VMSTATE_INT32
(
secs_cur
,
OneNANDState
),
VMSTATE_PARTIAL_VBUFFER
(
blockwp
,
OneNANDState
,
blocks
),
VMSTATE_UINT8
(
ecc
.
cp
,
OneNANDState
),
VMSTATE_UINT16_ARRAY
(
ecc
.
lp
,
OneNANDState
,
2
),
VMSTATE_UINT16
(
ecc
.
count
,
OneNANDState
),
VMSTATE_BUFFER_UNSAFE
(
otp
,
OneNANDState
,
0
,
((
64
+
2
)
<<
PAGE_SHIFT
)),
VMSTATE_END_OF_LIST
()
}
};
/* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
static
void
onenand_reset
(
OneNANDState
*
s
,
int
cold
)
{
...
...
@@ -167,11 +215,17 @@ static void onenand_reset(OneNANDState *s, int cold)
/* Lock the whole flash */
memset
(
s
->
blockwp
,
ONEN_LOCK_LOCKED
,
s
->
blocks
);
if
(
s
->
bdrv
&&
bdrv_read
(
s
->
bdrv
,
0
,
s
->
boot
[
0
],
8
)
<
0
)
hw_error
(
"%s: Loading the BootRAM failed.
\n
"
,
__FUNCTION__
);
if
(
s
->
bdrv_cur
&&
bdrv_read
(
s
->
bdrv_cur
,
0
,
s
->
boot
[
0
],
8
)
<
0
)
{
hw_error
(
"%s: Loading the BootRAM failed.
\n
"
,
__func__
);
}
}
}
static
void
onenand_system_reset
(
DeviceState
*
dev
)
{
onenand_reset
(
FROM_SYSBUS
(
OneNANDState
,
sysbus_from_qdev
(
dev
)),
1
);
}
static
inline
int
onenand_load_main
(
OneNANDState
*
s
,
int
sec
,
int
secn
,
void
*
dest
)
{
...
...
@@ -191,8 +245,8 @@ static inline int onenand_prog_main(OneNANDState *s, int sec, int secn,
int
result
=
0
;
if
(
secn
>
0
)
{
uint32_t
size
=
(
uint32_t
)
secn
*
512
;
const
uint8_t
*
sp
=
(
const
uint8_t
*
)
src
;
uint32_t
size
=
(
uint32_t
)
secn
*
512
;
const
uint8_t
*
sp
=
(
const
uint8_t
*
)
src
;
uint8_t
*
dp
=
0
;
if
(
s
->
bdrv_cur
)
{
dp
=
g_malloc
(
size
);
...
...
@@ -203,7 +257,7 @@ static inline int onenand_prog_main(OneNANDState *s, int sec, int secn,
if
(
sec
+
secn
>
s
->
secs_cur
)
{
result
=
1
;
}
else
{
dp
=
(
uint8_t
*
)
s
->
current
+
(
sec
<<
9
);
dp
=
(
uint8_t
*
)
s
->
current
+
(
sec
<<
9
);
}
}
if
(
!
result
)
{
...
...
@@ -245,13 +299,13 @@ static inline int onenand_prog_spare(OneNANDState *s, int sec, int secn,
{
int
result
=
0
;
if
(
secn
>
0
)
{
const
uint8_t
*
sp
=
(
const
uint8_t
*
)
src
;
const
uint8_t
*
sp
=
(
const
uint8_t
*
)
src
;
uint8_t
*
dp
=
0
,
*
dpp
=
0
;
if
(
s
->
bdrv_cur
)
{
dp
=
g_malloc
(
512
);
if
(
!
dp
||
bdrv_read
(
s
->
bdrv_cur
,
s
->
secs_cur
+
(
sec
>>
5
),
dp
,
1
)
<
0
)
{
s
->
secs_cur
+
(
sec
>>
5
),
dp
,
1
)
<
0
)
{
result
=
1
;
}
else
{
dpp
=
dp
+
((
sec
&
31
)
<<
4
);
...
...
@@ -270,7 +324,7 @@ static inline int onenand_prog_spare(OneNANDState *s, int sec, int secn,
}
if
(
s
->
bdrv_cur
)
{
result
=
bdrv_write
(
s
->
bdrv_cur
,
s
->
secs_cur
+
(
sec
>>
5
),
dp
,
1
)
<
0
;
dp
,
1
)
<
0
;
}
}
if
(
dp
)
{
...
...
@@ -326,7 +380,7 @@ fail:
return
1
;
}
static
void
onenand_command
(
OneNANDState
*
s
,
int
cmd
)
static
void
onenand_command
(
OneNANDState
*
s
)
{
int
b
;
int
sec
;
...
...
@@ -346,7 +400,7 @@ static void onenand_command(OneNANDState *s, int cmd)
s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
buf += (s->bufaddr & 3) << 4;
switch
(
cm
d
)
{
switch
(
s
->
comman
d
)
{
case
0x00
:
/* Load single/multiple sector data unit into buffer */
SETADDR
(
ONEN_BUF_BLOCK
,
ONEN_BUF_PAGE
)
...
...
@@ -527,7 +581,7 @@ static void onenand_command(OneNANDState *s, int cmd)
s
->
status
|=
ONEN_ERR_CMD
;
s
->
intstatus
|=
ONEN_INT
;
fprintf
(
stderr
,
"%s: unknown OneNAND command %x
\n
"
,
__
FUNCTION__
,
cm
d
);
__
func__
,
s
->
comman
d
);
}
onenand_intr_update
(
s
);
...
...
@@ -659,7 +713,7 @@ static void onenand_write(void *opaque, target_phys_addr_t addr,
if
(
s
->
intstatus
&
(
1
<<
15
))
break
;
s
->
command
=
value
;
onenand_command
(
s
,
s
->
command
);
onenand_command
(
s
);
break
;
case
0xf221
:
/* System Configuration 1 */
s
->
config
[
0
]
=
value
;
...
...
@@ -700,30 +754,25 @@ static const MemoryRegionOps onenand_ops = {
.
endianness
=
DEVICE_NATIVE_ENDIAN
,
};
void
*
onenand_init
(
BlockDriverState
*
bdrv
,
uint16_t
man_id
,
uint16_t
dev_id
,
uint16_t
ver_id
,
int
regshift
,
qemu_irq
irq
)
static
int
onenand_initfn
(
SysBusDevice
*
dev
)
{
OneNANDState
*
s
=
(
OneNANDState
*
)
g_malloc0
(
sizeof
(
*
s
))
;
uint32_t
size
=
1
<<
(
24
+
((
dev_id
>>
4
)
&
7
));
OneNANDState
*
s
=
(
OneNANDState
*
)
dev
;
uint32_t
size
=
1
<<
(
24
+
((
s
->
id
.
dev
>>
4
)
&
7
));
void
*
ram
;
s
->
shift
=
regshift
;
s
->
intr
=
irq
;
s
->
base
=
(
target_phys_addr_t
)
-
1
;
s
->
rdy
=
NULL
;
s
->
id
.
man
=
man_id
;
s
->
id
.
dev
=
dev_id
;
s
->
id
.
ver
=
ver_id
;
s
->
blocks
=
size
>>
BLOCK_SHIFT
;
s
->
secs
=
size
>>
9
;
s
->
blockwp
=
g_malloc
(
s
->
blocks
);
s
->
density_mask
=
(
dev_id
&
0x08
)
?
(
1
<<
(
6
+
((
dev_id
>>
4
)
&
7
)))
:
0
;
s
->
density_mask
=
(
s
->
id
.
dev
&
0x08
)
?
(
1
<<
(
6
+
((
s
->
id
.
dev
>>
4
)
&
7
)))
:
0
;
memory_region_init_io
(
&
s
->
iomem
,
&
onenand_ops
,
s
,
"onenand"
,
0x10000
<<
s
->
shift
);
s
->
bdrv
=
bdrv
;
if
(
!
s
->
bdrv
)
{
s
->
image
=
memset
(
g_malloc
(
size
+
(
size
>>
5
)),
0xff
,
size
+
(
size
>>
5
));
0xff
,
size
+
(
size
>>
5
));
}
else
{
s
->
bdrv_cur
=
s
->
bdrv
;
}
s
->
otp
=
memset
(
g_malloc
((
64
+
2
)
<<
PAGE_SHIFT
),
0xff
,
(
64
+
2
)
<<
PAGE_SHIFT
);
...
...
@@ -736,15 +785,40 @@ void *onenand_init(BlockDriverState *bdrv,
s
->
data
[
1
][
0
]
=
ram
+
((
0x0200
+
(
1
<<
(
PAGE_SHIFT
-
1
)))
<<
s
->
shift
);
s
->
data
[
1
][
1
]
=
ram
+
((
0x8010
+
(
1
<<
(
PAGE_SHIFT
-
6
)))
<<
s
->
shift
);
onenand_mem_setup
(
s
);
sysbus_init_irq
(
dev
,
&
s
->
intr
);
sysbus_init_mmio_region
(
dev
,
&
s
->
container
);
vmstate_register
(
&
dev
->
qdev
,
((
s
->
shift
&
0x7f
)
<<
24
)
|
((
s
->
id
.
man
&
0xff
)
<<
16
)
|
((
s
->
id
.
dev
&
0xff
)
<<
8
)
|
(
s
->
id
.
ver
&
0xff
),
&
vmstate_onenand
,
s
);
return
0
;
}
onenand_reset
(
s
,
1
);
static
SysBusDeviceInfo
onenand_info
=
{
.
init
=
onenand_initfn
,
.
qdev
.
name
=
"onenand"
,
.
qdev
.
size
=
sizeof
(
OneNANDState
),
.
qdev
.
reset
=
onenand_system_reset
,
.
qdev
.
props
=
(
Property
[])
{
DEFINE_PROP_UINT16
(
"manufacturer_id"
,
OneNANDState
,
id
.
man
,
0
),
DEFINE_PROP_UINT16
(
"device_id"
,
OneNANDState
,
id
.
dev
,
0
),
DEFINE_PROP_UINT16
(
"version_id"
,
OneNANDState
,
id
.
ver
,
0
),
DEFINE_PROP_INT32
(
"shift"
,
OneNANDState
,
shift
,
0
),
DEFINE_PROP_DRIVE
(
"drive"
,
OneNANDState
,
bdrv
),
DEFINE_PROP_END_OF_LIST
()
}
};
return
s
;
static
void
onenand_register_device
(
void
)
{
sysbus_register_withprop
(
&
onenand_info
);
}
void
*
onenand_raw_otp
(
void
*
opaqu
e
)
void
*
onenand_raw_otp
(
DeviceState
*
onenand_devic
e
)
{
OneNANDState
*
s
=
(
OneNANDState
*
)
opaque
;
return
s
->
otp
;
return
FROM_SYSBUS
(
OneNANDState
,
sysbus_from_qdev
(
onenand_device
))
->
otp
;
}
device_init
(
onenand_register_device
)
hw/sysbus.c
浏览文件 @
f0fb8b71
...
...
@@ -131,6 +131,11 @@ void sysbus_init_mmio_region(SysBusDevice *dev, MemoryRegion *memory)
dev
->
mmio
[
n
].
memory
=
memory
;
}
MemoryRegion
*
sysbus_mmio_get_region
(
SysBusDevice
*
dev
,
int
n
)
{
return
dev
->
mmio
[
n
].
memory
;
}
void
sysbus_init_ioports
(
SysBusDevice
*
dev
,
pio_addr_t
ioport
,
pio_addr_t
size
)
{
pio_addr_t
i
;
...
...
hw/sysbus.h
浏览文件 @
f0fb8b71
...
...
@@ -50,6 +50,7 @@ void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size,
void
sysbus_init_mmio_cb2
(
SysBusDevice
*
dev
,
mmio_mapfunc
cb
,
mmio_mapfunc
unmap
);
void
sysbus_init_mmio_region
(
SysBusDevice
*
dev
,
MemoryRegion
*
memory
);
MemoryRegion
*
sysbus_mmio_get_region
(
SysBusDevice
*
dev
,
int
n
);
void
sysbus_init_irq
(
SysBusDevice
*
dev
,
qemu_irq
*
p
);
void
sysbus_pass_irq
(
SysBusDevice
*
dev
,
SysBusDevice
*
target
);
void
sysbus_init_ioports
(
SysBusDevice
*
dev
,
pio_addr_t
ioport
,
pio_addr_t
size
);
...
...
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