diff --git a/hw/cs4231.c b/hw/cs4231.c index 8ba8253945718f691ea80ea21f6f098e415293ec..d53f194a5b79cf101671fb5790d3fd1ee3f4826f 100644 --- a/hw/cs4231.c +++ b/hw/cs4231.c @@ -30,8 +30,7 @@ /* * In addition to Crystal CS4231 there is a DMA controller on Sparc. */ -#define CS_MAXADDR 0x3f -#define CS_SIZE (CS_MAXADDR + 1) +#define CS_SIZE 0x40 #define CS_REGS 16 #define CS_DREGS 32 #define CS_MAXDREG (CS_DREGS - 1) @@ -68,7 +67,7 @@ static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr) CSState *s = opaque; uint32_t saddr, ret; - saddr = (addr & CS_MAXADDR) >> 2; + saddr = addr >> 2; switch (saddr) { case 1: switch (CS_RAP(s)) { @@ -94,7 +93,7 @@ static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) CSState *s = opaque; uint32_t saddr; - saddr = (addr & CS_MAXADDR) >> 2; + saddr = addr >> 2; DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val); switch (saddr) { case 1: diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c index 5ee50aee020af2e44ba72b62a56cd2e4077f7e81..0f28573b25cb33d5f0f93e68b8461f39d00ec087 100644 --- a/hw/eccmemctl.c +++ b/hw/eccmemctl.c @@ -114,7 +114,6 @@ #define ECC_NREGS 9 #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) -#define ECC_ADDR_MASK 0x1f #define ECC_DIAG_SIZE 4 #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) @@ -129,7 +128,7 @@ static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { ECCState *s = opaque; - switch ((addr & ECC_ADDR_MASK) >> 2) { + switch (addr >> 2) { case ECC_MER: s->regs[ECC_MER] = (s->regs[ECC_MER] & (ECC_MER_VER | ECC_MER_IMPL)) | (val & ~(ECC_MER_VER | ECC_MER_IMPL)); @@ -167,7 +166,7 @@ static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr) ECCState *s = opaque; uint32_t ret = 0; - switch ((addr & ECC_ADDR_MASK) >> 2) { + switch (addr >> 2) { case ECC_MER: ret = s->regs[ECC_MER]; DPRINTF("Read memory enable %08x\n", ret); @@ -225,15 +224,16 @@ static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr, { ECCState *s = opaque; - DPRINTF("Write diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), val); + DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val); s->diag[addr & ECC_DIAG_MASK] = val; } static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr) { ECCState *s = opaque; - uint32_t ret = s->diag[addr & ECC_DIAG_MASK]; - DPRINTF("Read diagnostic[%d] = %02x\n", (int)(addr & ECC_DIAG_MASK), ret); + uint32_t ret = s->diag[(int)addr]; + + DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret); return ret; } diff --git a/hw/esp.c b/hw/esp.c index d28229c4a7d012172b830371f212b0383eb71dd2..c3dbae001f74c6f7101df9d3d9b7d9614f851a88 100644 --- a/hw/esp.c +++ b/hw/esp.c @@ -425,7 +425,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) ESPState *s = opaque; uint32_t saddr; - saddr = (addr >> s->it_shift) & (ESP_REGS - 1); + saddr = addr >> s->it_shift; DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]); switch (saddr) { case ESP_FIFO: @@ -461,7 +461,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) ESPState *s = opaque; uint32_t saddr; - saddr = (addr >> s->it_shift) & (ESP_REGS - 1); + saddr = addr >> s->it_shift; DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val); switch (saddr) { diff --git a/hw/fdc.c b/hw/fdc.c index cd00420bd522586feddfb3c5184a0ff3993ede55..26ff1842509639bbdecc24988d42abea99d51beb 100644 --- a/hw/fdc.c +++ b/hw/fdc.c @@ -513,7 +513,7 @@ static uint32_t fdctrl_read (void *opaque, uint32_t reg) fdctrl_t *fdctrl = opaque; uint32_t retval; - switch (reg & 0x07) { + switch (reg) { case FD_REG_SRA: retval = fdctrl_read_statusA(fdctrl); break; @@ -550,7 +550,7 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); - switch (reg & 0x07) { + switch (reg) { case FD_REG_DOR: fdctrl_write_dor(fdctrl, value); break; @@ -568,6 +568,16 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) } } +static uint32_t fdctrl_read_port (void *opaque, uint32_t reg) +{ + return fdctrl_read(opaque, reg & 7); +} + +static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value) +{ + fdctrl_write(opaque, reg & 7, value); +} + static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg) { return fdctrl_read(opaque, (uint32_t)reg); @@ -1896,14 +1906,14 @@ fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, fdctrl); cpu_register_physical_memory(io_base, 0x08, io_mem); } else { - register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read, - fdctrl); - register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read, - fdctrl); - register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write, - fdctrl); - register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write, - fdctrl); + register_ioport_read((uint32_t)io_base + 0x01, 5, 1, + &fdctrl_read_port, fdctrl); + register_ioport_read((uint32_t)io_base + 0x07, 1, 1, + &fdctrl_read_port, fdctrl); + register_ioport_write((uint32_t)io_base + 0x01, 5, 1, + &fdctrl_write_port, fdctrl); + register_ioport_write((uint32_t)io_base + 0x07, 1, 1, + &fdctrl_write_port, fdctrl); } return fdctrl; diff --git a/hw/pcnet.c b/hw/pcnet.c index 188e5ffd3b6386d459f97bc46eb0d9b2679262b6..30c453c937bc5f074cede4cf05440562f636e1f0 100644 --- a/hw/pcnet.c +++ b/hw/pcnet.c @@ -2060,14 +2060,14 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr, val & 0xffff); #endif - pcnet_ioport_writew(opaque, addr & 7, val & 0xffff); + pcnet_ioport_writew(opaque, addr, val & 0xffff); } static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr) { uint32_t val; - val = pcnet_ioport_readw(opaque, addr & 7); + val = pcnet_ioport_readw(opaque, addr); #ifdef PCNET_DEBUG_IO printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr, val & 0xffff); diff --git a/hw/sbi.c b/hw/sbi.c index 8d264f1aab89c7894daccb37a7b960ca39dab12c..199db8fdc326847932b5f465a83ada08c05ad6af 100644 --- a/hw/sbi.c +++ b/hw/sbi.c @@ -46,7 +46,6 @@ typedef struct SBIState { } SBIState; #define SBI_SIZE (SBI_NREGS * 4) -#define SBI_MASK (SBI_SIZE - 1) static void sbi_check_interrupts(void *opaque) { @@ -65,7 +64,7 @@ static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr) SBIState *s = opaque; uint32_t saddr, ret; - saddr = (addr & SBI_MASK) >> 2; + saddr = addr >> 2; switch (saddr) { default: ret = s->regs[saddr]; @@ -81,7 +80,7 @@ static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) SBIState *s = opaque; uint32_t saddr; - saddr = (addr & SBI_MASK) >> 2; + saddr = addr >> 2; DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); switch (saddr) { default: diff --git a/hw/slavio_serial.c b/hw/slavio_serial.c index 9f5843af687d6d002d18c8c6b08327240f124b27..1028ed944c71508d7c1130daeeac8dbba2563e28 100644 --- a/hw/slavio_serial.c +++ b/hw/slavio_serial.c @@ -108,8 +108,7 @@ struct SerialState { struct ChannelState chn[2]; }; -#define SERIAL_MAXADDR 7 -#define SERIAL_SIZE (SERIAL_MAXADDR + 1) +#define SERIAL_SIZE 8 #define SERIAL_CTRL 0 #define SERIAL_DATA 1 @@ -477,7 +476,7 @@ static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, val &= 0xff; saddr = (addr & 3) >> 1; - channel = (addr & SERIAL_MAXADDR) >> 2; + channel = addr >> 2; s = &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: @@ -574,7 +573,7 @@ static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr) int channel; saddr = (addr & 3) >> 1; - channel = (addr & SERIAL_MAXADDR) >> 2; + channel = addr >> 2; s = &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c index f091fbe5f9490e71d65af20f51cc531e4b371c87..01cb1cf6a6043002422375a25fb660dd5a309d97 100644 --- a/hw/slavio_timer.c +++ b/hw/slavio_timer.c @@ -66,7 +66,6 @@ typedef struct SLAVIO_TIMERState { uint32_t slave_mode; } SLAVIO_TIMERState; -#define TIMER_MAXADDR 0x1f #define SYS_TIMER_SIZE 0x14 #define CPU_TIMER_SIZE 0x10 @@ -132,7 +131,7 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) SLAVIO_TIMERState *s = opaque; uint32_t saddr, ret; - saddr = (addr & TIMER_MAXADDR) >> 2; + saddr = addr >> 2; switch (saddr) { case TIMER_LIMIT: // read limit (system counter mode) or read most signifying @@ -185,7 +184,7 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t saddr; DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val); - saddr = (addr & TIMER_MAXADDR) >> 2; + saddr = addr >> 2; switch (saddr) { case TIMER_LIMIT: if (slavio_timer_is_user(s)) { diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c index c69b559becd37af9efb3e5b00e954841c4828ceb..e12216d60a755b57d8252533eebe061ca4118d20 100644 --- a/hw/sparc32_dma.c +++ b/hw/sparc32_dma.c @@ -45,7 +45,6 @@ do { printf("DMA: " fmt , ##args); } while (0) #define DMA_REGS 4 #define DMA_SIZE (4 * sizeof(uint32_t)) -#define DMA_MAXADDR (DMA_SIZE - 1) #define DMA_VER 0xa0000000 #define DMA_INTR 1 @@ -157,7 +156,7 @@ static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr) DMAState *s = opaque; uint32_t saddr; - saddr = (addr & DMA_MAXADDR) >> 2; + saddr = addr >> 2; DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr, s->dmaregs[saddr]); @@ -169,7 +168,7 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) DMAState *s = opaque; uint32_t saddr; - saddr = (addr & DMA_MAXADDR) >> 2; + saddr = addr >> 2; DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr, s->dmaregs[saddr], val); switch (saddr) { diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c index 88cd4a53bd06881f9afcdf80084c4982a7047152..c8c40c9f05c4951fa573e5acbe5531b6943b7ea5 100644 --- a/hw/sun4c_intctl.c +++ b/hw/sun4c_intctl.c @@ -52,8 +52,7 @@ typedef struct Sun4c_INTCTLState { uint8_t pending; } Sun4c_INTCTLState; -#define INTCTL_MAXADDR 0 -#define INTCTL_SIZE (INTCTL_MAXADDR + 1) +#define INTCTL_SIZE 1 static void sun4c_check_interrupts(void *opaque); diff --git a/hw/tcx.c b/hw/tcx.c index de4fda0b42a49dc482234407c954b387c51675d0..004685bc2b295e63c4105e72bc841a5a97d3e64f 100644 --- a/hw/tcx.c +++ b/hw/tcx.c @@ -437,15 +437,13 @@ static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { TCXState *s = opaque; - uint32_t saddr; - saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2; - switch (saddr) { + switch (addr) { case 0: s->dac_index = val >> 24; s->dac_state = 0; break; - case 1: + case 4: switch (s->dac_state) { case 0: s->r[s->dac_index] = val >> 24;