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提交 d63001d1 编写于 作者: J j_mayer
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Make PowerPC cache line size implementation dependant. 

Implement dcbz tunable cache line size for PowerPC 970.
Make hardware reset vector implementation dependant.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3321 c046a42c-6fe2-441c-8c8c-71466251a162
上级 06403421
展开全部 显示空白变更内容
内联 并排
Showing with 620 addition and 60 deletion
target-ppc/cpu.h
浏览文件 @ d63001d1
......@@ -82,12 +82,6 @@ typedef uint32_t ppc_gpr_t;
#define ELF_MACHINE EM_PPC
#endif
/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
* have different cache line sizes
*/
#define ICACHE_LINE_SIZE 32
#define DCACHE_LINE_SIZE 32
/*****************************************************************************/
/* MMU model */
enum {
......@@ -521,6 +515,9 @@ struct CPUPPCState {
/* 403 dedicated access protection registers */
target_ulong pb[4];
int dcache_line_size;
int icache_line_size;
/* Those resources are used during exception processing */
/* CPU model definition */
target_ulong msr_mask;
......@@ -546,6 +543,7 @@ struct CPUPPCState {
target_ulong excp_prefix;
target_ulong ivor_mask;
target_ulong ivpr_mask;
target_ulong hreset_vector;
#endif
/* Those resources are used only during code translation */
......@@ -1052,6 +1050,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
#define SPR_601_HID5 (0x3F5)
#define SPR_40x_DAC1 (0x3F6)
#define SPR_MSSCR0 (0x3F6)
#define SPR_970_HID5 (0x3F6)
#define SPR_MSSSR0 (0x3F7)
#define SPR_DABRX (0x3F7)
#define SPR_40x_DAC2 (0x3F7)
......
target-ppc/op_helper.c
浏览文件 @ d63001d1
......@@ -1061,21 +1061,21 @@ void do_POWER_clcs (void)
switch (T0) {
case 0x0CUL:
/* Instruction cache line size */
T0 = ICACHE_LINE_SIZE;
T0 = env->icache_line_size;
break;
case 0x0DUL:
/* Data cache line size */
T0 = DCACHE_LINE_SIZE;
T0 = env->dcache_line_size;
break;
case 0x0EUL:
/* Minimum cache line size */
T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
T0 = env->icache_line_size < env->dcache_line_size ?
env->icache_line_size : env->dcache_line_size;
break;
case 0x0FUL:
/* Maximum cache line size */
T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
T0 = env->icache_line_size > env->dcache_line_size ?
env->icache_line_size : env->dcache_line_size;
break;
default:
/* Undefined */
......
target-ppc/op_helper.h
浏览文件 @ d63001d1
......@@ -30,6 +30,7 @@ void glue(do_lmw_le, MEMSUFFIX) (int dst);
void glue(do_stmw, MEMSUFFIX) (int src);
void glue(do_stmw_le, MEMSUFFIX) (int src);
void glue(do_icbi, MEMSUFFIX) (void);
void glue(do_dcbz, MEMSUFFIX) (void);
void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb);
void glue(do_POWER2_lfq, MEMSUFFIX) (void);
void glue(do_POWER2_lfq_le, MEMSUFFIX) (void);
......@@ -46,6 +47,7 @@ void glue(do_lmw_le_64, MEMSUFFIX) (int dst);
void glue(do_stmw_64, MEMSUFFIX) (int src);
void glue(do_stmw_le_64, MEMSUFFIX) (int src);
void glue(do_icbi_64, MEMSUFFIX) (void);
void glue(do_dcbz_64, MEMSUFFIX) (void);
#endif
#else
......
target-ppc/op_helper_mem.h
浏览文件 @ d63001d1
......@@ -252,8 +252,9 @@ void glue(do_icbi, MEMSUFFIX) (void)
* do the load "by hand".
*/
tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);
T0 &= ~(ICACHE_LINE_SIZE - 1);
tb_invalidate_page_range((uint32_t)T0, (uint32_t)(T0 + ICACHE_LINE_SIZE));
T0 &= ~(env->icache_line_size - 1);
tb_invalidate_page_range((uint32_t)T0,
(uint32_t)(T0 + env->icache_line_size));
}
#if defined(TARGET_PPC64)
......@@ -266,8 +267,101 @@ void glue(do_icbi_64, MEMSUFFIX) (void)
* do the load "by hand".
*/
tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);
T0 &= ~(ICACHE_LINE_SIZE - 1);
tb_invalidate_page_range((uint64_t)T0, (uint64_t)(T0 + ICACHE_LINE_SIZE));
T0 &= ~(env->icache_line_size - 1);
tb_invalidate_page_range((uint64_t)T0,
(uint64_t)(T0 + env->icache_line_size));
}
#endif
void glue(do_dcbz, MEMSUFFIX) (void)
{
int dcache_line_size = env->dcache_line_size;
/* XXX: should be 970 specific (?) */
if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
dcache_line_size = 32;
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
if (dcache_line_size >= 64) {
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x2CUL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x30UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0);
if (dcache_line_size >= 128) {
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x40UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x44UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x48UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x4CUL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x50UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x54UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x58UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x5CUL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x60UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x64UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x68UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x6CUL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x70UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x74UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x78UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x7CUL), 0);
}
}
}
#if defined(TARGET_PPC64)
void glue(do_dcbz_64, MEMSUFFIX) (void)
{
int dcache_line_size = env->dcache_line_size;
/* XXX: should be 970 specific (?) */
if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
dcache_line_size = 32;
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
if (dcache_line_size >= 64) {
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x2CUL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x30UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0);
if (dcache_line_size >= 128) {
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x40UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x44UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x48UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x4CUL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x50UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x54UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x58UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x5CUL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x60UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x64UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x68UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x6CUL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x70UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x74UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x78UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x7CUL), 0);
}
}
}
#endif
......
target-ppc/op_mem.h
浏览文件 @ d63001d1
......@@ -787,7 +787,20 @@ void OPPROTO glue(op_stdcx_le_64, MEMSUFFIX) (void)
}
#endif
void OPPROTO glue(op_dcbz, MEMSUFFIX) (void)
void OPPROTO glue(op_dcbz_l32, MEMSUFFIX) (void)
{
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
RETURN();
}
void OPPROTO glue(op_dcbz_l64, MEMSUFFIX) (void)
{
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
......@@ -797,8 +810,6 @@ void OPPROTO glue(op_dcbz, MEMSUFFIX) (void)
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
#if DCACHE_LINE_SIZE == 64
/* XXX: cache line size should be 64 for POWER & PowerPC 601 */
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0);
......@@ -807,12 +818,67 @@ void OPPROTO glue(op_dcbz, MEMSUFFIX) (void)
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0);
#endif
RETURN();
}
void OPPROTO glue(op_dcbz_l128, MEMSUFFIX) (void)
{
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x2CUL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x30UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x40UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x44UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x48UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x4CUL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x50UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x54UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x58UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x5CUL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x60UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x64UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x68UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x6CUL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x70UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x74UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x78UL), 0);
glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x7CUL), 0);
RETURN();
}
void OPPROTO glue(op_dcbz, MEMSUFFIX) (void)
{
glue(do_dcbz, MEMSUFFIX)();
RETURN();
}
#if defined(TARGET_PPC64)
void OPPROTO glue(op_dcbz_64, MEMSUFFIX) (void)
void OPPROTO glue(op_dcbz_l32_64, MEMSUFFIX) (void)
{
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
RETURN();
}
void OPPROTO glue(op_dcbz_l64_64, MEMSUFFIX) (void)
{
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
......@@ -822,8 +888,6 @@ void OPPROTO glue(op_dcbz_64, MEMSUFFIX) (void)
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
#if DCACHE_LINE_SIZE == 64
/* XXX: cache line size should be 64 for POWER & PowerPC 601 */
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0);
......@@ -832,7 +896,49 @@ void OPPROTO glue(op_dcbz_64, MEMSUFFIX) (void)
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0);
#endif
RETURN();
}
void OPPROTO glue(op_dcbz_l128_64, MEMSUFFIX) (void)
{
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x2CUL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x30UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x40UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x44UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x48UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x4CUL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x50UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x54UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x58UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x5CUL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x60UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x64UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x68UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x6CUL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x70UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x74UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x78UL), 0);
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x7CUL), 0);
RETURN();
}
void OPPROTO glue(op_dcbz_64, MEMSUFFIX) (void)
{
glue(do_dcbz_64, MEMSUFFIX)();
RETURN();
}
#endif
......
target-ppc/translate.c
浏览文件 @ d63001d1
......@@ -169,6 +169,7 @@ typedef struct DisasContext {
#endif
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
int dcache_line_size;
} DisasContext;
struct opc_handler_t {
......@@ -482,6 +483,10 @@ enum {
PPC_WAIT = 0x0000100000000000ULL,
/* New 64 bits extensions (PowerPC 2.0x) */
PPC_64BX = 0x0000200000000000ULL,
/* dcbz instruction with fixed cache line size */
PPC_CACHE_DCBZ = 0x0000400000000000ULL,
/* dcbz instruction with tunable cache line size */
PPC_CACHE_DCBZT = 0x0000800000000000ULL,
};
/*****************************************************************************/
......@@ -3623,21 +3628,96 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
}
/* dcbz */
#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
#if defined(CONFIG_USER_ONLY)
/* User-mode only */
static GenOpFunc *gen_op_dcbz[] = {
static GenOpFunc *gen_op_dcbz[4][4] = {
{
&gen_op_dcbz_l32_raw,
&gen_op_dcbz_l32_raw,
#if defined(TARGET_PPC64)
&gen_op_dcbz_l32_64_raw,
&gen_op_dcbz_l32_64_raw,
#endif
},
{
&gen_op_dcbz_l64_raw,
&gen_op_dcbz_l64_raw,
#if defined(TARGET_PPC64)
&gen_op_dcbz_l64_64_raw,
&gen_op_dcbz_l64_64_raw,
#endif
},
{
&gen_op_dcbz_l128_raw,
&gen_op_dcbz_l128_raw,
#if defined(TARGET_PPC64)
&gen_op_dcbz_l128_64_raw,
&gen_op_dcbz_l128_64_raw,
#endif
},
{
&gen_op_dcbz_raw,
&gen_op_dcbz_raw,
#if defined(TARGET_PPC64)
&gen_op_dcbz_64_raw,
&gen_op_dcbz_64_raw,
#endif
},
};
#else
#if defined(TARGET_PPC64)
/* Full system - 64 bits mode */
static GenOpFunc *gen_op_dcbz[] = {
static GenOpFunc *gen_op_dcbz[4][12] = {
{
&gen_op_dcbz_l32_user,
&gen_op_dcbz_l32_user,
&gen_op_dcbz_l32_64_user,
&gen_op_dcbz_l32_64_user,
&gen_op_dcbz_l32_kernel,
&gen_op_dcbz_l32_kernel,
&gen_op_dcbz_l32_64_kernel,
&gen_op_dcbz_l32_64_kernel,
#if defined(TARGET_PPC64H)
&gen_op_dcbz_l32_hypv,
&gen_op_dcbz_l32_hypv,
&gen_op_dcbz_l32_64_hypv,
&gen_op_dcbz_l32_64_hypv,
#endif
},
{
&gen_op_dcbz_l64_user,
&gen_op_dcbz_l64_user,
&gen_op_dcbz_l64_64_user,
&gen_op_dcbz_l64_64_user,
&gen_op_dcbz_l64_kernel,
&gen_op_dcbz_l64_kernel,
&gen_op_dcbz_l64_64_kernel,
&gen_op_dcbz_l64_64_kernel,
#if defined(TARGET_PPC64H)
&gen_op_dcbz_l64_hypv,
&gen_op_dcbz_l64_hypv,
&gen_op_dcbz_l64_64_hypv,
&gen_op_dcbz_l64_64_hypv,
#endif
},
{
&gen_op_dcbz_l128_user,
&gen_op_dcbz_l128_user,
&gen_op_dcbz_l128_64_user,
&gen_op_dcbz_l128_64_user,
&gen_op_dcbz_l128_kernel,
&gen_op_dcbz_l128_kernel,
&gen_op_dcbz_l128_64_kernel,
&gen_op_dcbz_l128_64_kernel,
#if defined(TARGET_PPC64H)
&gen_op_dcbz_l128_hypv,
&gen_op_dcbz_l128_hypv,
&gen_op_dcbz_l128_64_hypv,
&gen_op_dcbz_l128_64_hypv,
#endif
},
{
&gen_op_dcbz_user,
&gen_op_dcbz_user,
&gen_op_dcbz_64_user,
......@@ -3652,22 +3732,74 @@ static GenOpFunc *gen_op_dcbz[] = {
&gen_op_dcbz_64_hypv,
&gen_op_dcbz_64_hypv,
#endif
},
};
#else
/* Full system - 32 bits mode */
static GenOpFunc *gen_op_dcbz[] = {
static GenOpFunc *gen_op_dcbz[4][4] = {
{
&gen_op_dcbz_l32_user,
&gen_op_dcbz_l32_user,
&gen_op_dcbz_l32_kernel,
&gen_op_dcbz_l32_kernel,
},
{
&gen_op_dcbz_l64_user,
&gen_op_dcbz_l64_user,
&gen_op_dcbz_l64_kernel,
&gen_op_dcbz_l64_kernel,
},
{
&gen_op_dcbz_l128_user,
&gen_op_dcbz_l128_user,
&gen_op_dcbz_l128_kernel,
&gen_op_dcbz_l128_kernel,
},
{
&gen_op_dcbz_user,
&gen_op_dcbz_user,
&gen_op_dcbz_kernel,
&gen_op_dcbz_kernel,
},
};
#endif
#endif
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
static inline void handler_dcbz (DisasContext *ctx, int dcache_line_size)
{
int n;
switch (dcache_line_size) {
case 32:
n = 0;
break;
case 64:
n = 1;
break;
case 128:
n = 2;
break;
default:
n = 3;
break;
}
op_dcbz(n);
}
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
{
gen_addr_reg_index(ctx);
op_dcbz();
handler_dcbz(ctx, ctx->dcache_line_size);
gen_op_check_reservation();
}
GEN_HANDLER(dcbz_970, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
{
gen_addr_reg_index(ctx);
if (ctx->opcode & 0x00200000)
handler_dcbz(ctx, ctx->dcache_line_size);
else
handler_dcbz(ctx, -1);
gen_op_check_reservation();
}
......@@ -6341,6 +6473,7 @@ static inline int gen_intermediate_code_internal (CPUState *env,
#else
ctx.mem_idx = (supervisor << 1) | msr_le;
#endif
ctx.dcache_line_size = env->dcache_line_size;
ctx.fpu_enabled = msr_fp;
#if defined(TARGET_PPCEMB)
ctx.spe_enabled = msr_spe;
......
target-ppc/translate_init.c
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