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体验新版 GitCode,发现更多精彩内容 >>
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adfc39ea
编写于
9月 25, 2011
作者:
A
Avi Kivity
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
pxa2xx: convert to memory API (part II)
Signed-off-by:
N
Avi Kivity
<
avi@redhat.com
>
上级
9c843933
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
66 addition
and
87 deletion
+66
-87
hw/pxa.h
hw/pxa.h
+5
-0
hw/pxa2xx.c
hw/pxa2xx.c
+61
-87
未找到文件。
hw/pxa.h
浏览文件 @
adfc39ea
...
...
@@ -122,6 +122,11 @@ typedef struct {
CPUState
*
env
;
DeviceState
*
pic
;
qemu_irq
reset
;
MemoryRegion
sdram
;
MemoryRegion
internal
;
MemoryRegion
cm_iomem
;
MemoryRegion
mm_iomem
;
MemoryRegion
pm_iomem
;
DeviceState
*
dma
;
DeviceState
*
gpio
;
PXA2xxLCDState
*
lcd
;
...
...
hw/pxa2xx.c
浏览文件 @
adfc39ea
...
...
@@ -88,7 +88,8 @@ static PXASSPDef pxa27x_ssp[] = {
#define PCMD0 0x80
/* Power Manager I2C Command register File 0 */
#define PCMD31 0xfc
/* Power Manager I2C Command register File 31 */
static
uint32_t
pxa2xx_pm_read
(
void
*
opaque
,
target_phys_addr_t
addr
)
static
uint64_t
pxa2xx_pm_read
(
void
*
opaque
,
target_phys_addr_t
addr
,
unsigned
size
)
{
PXA2xxState
*
s
=
(
PXA2xxState
*
)
opaque
;
...
...
@@ -107,7 +108,7 @@ static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
}
static
void
pxa2xx_pm_write
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
valu
e
)
uint64_t
value
,
unsigned
siz
e
)
{
PXA2xxState
*
s
=
(
PXA2xxState
*
)
opaque
;
...
...
@@ -134,16 +135,10 @@ static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
}
}
static
CPUReadMemoryFunc
*
const
pxa2xx_pm_readfn
[]
=
{
pxa2xx_pm_read
,
pxa2xx_pm_read
,
pxa2xx_pm_read
,
};
static
CPUWriteMemoryFunc
*
const
pxa2xx_pm_writefn
[]
=
{
pxa2xx_pm_write
,
pxa2xx_pm_write
,
pxa2xx_pm_write
,
static
const
MemoryRegionOps
pxa2xx_pm_ops
=
{
.
read
=
pxa2xx_pm_read
,
.
write
=
pxa2xx_pm_write
,
.
endianness
=
DEVICE_NATIVE_ENDIAN
,
};
static
const
VMStateDescription
vmstate_pxa2xx_pm
=
{
...
...
@@ -162,7 +157,8 @@ static const VMStateDescription vmstate_pxa2xx_pm = {
#define OSCC 0x08
/* Oscillator Configuration register */
#define CCSR 0x0c
/* Core Clock Status register */
static
uint32_t
pxa2xx_cm_read
(
void
*
opaque
,
target_phys_addr_t
addr
)
static
uint64_t
pxa2xx_cm_read
(
void
*
opaque
,
target_phys_addr_t
addr
,
unsigned
size
)
{
PXA2xxState
*
s
=
(
PXA2xxState
*
)
opaque
;
...
...
@@ -183,7 +179,7 @@ static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
}
static
void
pxa2xx_cm_write
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
valu
e
)
uint64_t
value
,
unsigned
siz
e
)
{
PXA2xxState
*
s
=
(
PXA2xxState
*
)
opaque
;
...
...
@@ -206,16 +202,10 @@ static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
}
}
static
CPUReadMemoryFunc
*
const
pxa2xx_cm_readfn
[]
=
{
pxa2xx_cm_read
,
pxa2xx_cm_read
,
pxa2xx_cm_read
,
};
static
CPUWriteMemoryFunc
*
const
pxa2xx_cm_writefn
[]
=
{
pxa2xx_cm_write
,
pxa2xx_cm_write
,
pxa2xx_cm_write
,
static
const
MemoryRegionOps
pxa2xx_cm_ops
=
{
.
read
=
pxa2xx_cm_read
,
.
write
=
pxa2xx_cm_write
,
.
endianness
=
DEVICE_NATIVE_ENDIAN
,
};
static
const
VMStateDescription
vmstate_pxa2xx_cm
=
{
...
...
@@ -461,7 +451,8 @@ static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
#define BSCNTR3 0x60
/* Memory Buffer Strength Control register 3 */
#define SA1110 0x64
/* SA-1110 Memory Compatibility register */
static
uint32_t
pxa2xx_mm_read
(
void
*
opaque
,
target_phys_addr_t
addr
)
static
uint64_t
pxa2xx_mm_read
(
void
*
opaque
,
target_phys_addr_t
addr
,
unsigned
size
)
{
PXA2xxState
*
s
=
(
PXA2xxState
*
)
opaque
;
...
...
@@ -478,7 +469,7 @@ static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
}
static
void
pxa2xx_mm_write
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
valu
e
)
uint64_t
value
,
unsigned
siz
e
)
{
PXA2xxState
*
s
=
(
PXA2xxState
*
)
opaque
;
...
...
@@ -495,16 +486,10 @@ static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
}
}
static
CPUReadMemoryFunc
*
const
pxa2xx_mm_readfn
[]
=
{
pxa2xx_mm_read
,
pxa2xx_mm_read
,
pxa2xx_mm_read
,
};
static
CPUWriteMemoryFunc
*
const
pxa2xx_mm_writefn
[]
=
{
pxa2xx_mm_write
,
pxa2xx_mm_write
,
pxa2xx_mm_write
,
static
const
MemoryRegionOps
pxa2xx_mm_ops
=
{
.
read
=
pxa2xx_mm_read
,
.
write
=
pxa2xx_mm_write
,
.
endianness
=
DEVICE_NATIVE_ENDIAN
,
};
static
const
VMStateDescription
vmstate_pxa2xx_mm
=
{
...
...
@@ -1764,6 +1749,7 @@ static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
/* PXA Fast Infra-red Communications Port */
struct
PXA2xxFIrState
{
MemoryRegion
iomem
;
qemu_irq
irq
;
qemu_irq
rx_dma
;
qemu_irq
tx_dma
;
...
...
@@ -1834,7 +1820,8 @@ static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
#define ICSR1 0x18
/* FICP Status register 1 */
#define ICFOR 0x1c
/* FICP FIFO Occupancy Status register */
static
uint32_t
pxa2xx_fir_read
(
void
*
opaque
,
target_phys_addr_t
addr
)
static
uint64_t
pxa2xx_fir_read
(
void
*
opaque
,
target_phys_addr_t
addr
,
unsigned
size
)
{
PXA2xxFIrState
*
s
=
(
PXA2xxFIrState
*
)
opaque
;
uint8_t
ret
;
...
...
@@ -1872,9 +1859,10 @@ static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
}
static
void
pxa2xx_fir_write
(
void
*
opaque
,
target_phys_addr_t
addr
,
uint32_t
valu
e
)
uint64_t
value64
,
unsigned
siz
e
)
{
PXA2xxFIrState
*
s
=
(
PXA2xxFIrState
*
)
opaque
;
uint32_t
value
=
value64
;
uint8_t
ch
;
switch
(
addr
)
{
...
...
@@ -1916,16 +1904,10 @@ static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
}
}
static
CPUReadMemoryFunc
*
const
pxa2xx_fir_readfn
[]
=
{
pxa2xx_fir_read
,
pxa2xx_fir_read
,
pxa2xx_fir_read
,
};
static
CPUWriteMemoryFunc
*
const
pxa2xx_fir_writefn
[]
=
{
pxa2xx_fir_write
,
pxa2xx_fir_write
,
pxa2xx_fir_write
,
static
const
MemoryRegionOps
pxa2xx_fir_ops
=
{
.
read
=
pxa2xx_fir_read
,
.
write
=
pxa2xx_fir_write
,
.
endianness
=
DEVICE_NATIVE_ENDIAN
,
};
static
int
pxa2xx_fir_is_empty
(
void
*
opaque
)
...
...
@@ -1999,11 +1981,11 @@ static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
return
0
;
}
static
PXA2xxFIrState
*
pxa2xx_fir_init
(
target_phys_addr_t
base
,
static
PXA2xxFIrState
*
pxa2xx_fir_init
(
MemoryRegion
*
sysmem
,
target_phys_addr_t
base
,
qemu_irq
irq
,
qemu_irq
rx_dma
,
qemu_irq
tx_dma
,
CharDriverState
*
chr
)
{
int
iomemtype
;
PXA2xxFIrState
*
s
=
(
PXA2xxFIrState
*
)
g_malloc0
(
sizeof
(
PXA2xxFIrState
));
...
...
@@ -2014,9 +1996,8 @@ static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
pxa2xx_fir_reset
(
s
);
iomemtype
=
cpu_register_io_memory
(
pxa2xx_fir_readfn
,
pxa2xx_fir_writefn
,
s
,
DEVICE_NATIVE_ENDIAN
);
cpu_register_physical_memory
(
base
,
0x1000
,
iomemtype
);
memory_region_init_io
(
&
s
->
iomem
,
&
pxa2xx_fir_ops
,
s
,
"pxa2xx-fir"
,
0x1000
);
memory_region_add_subregion
(
sysmem
,
base
,
&
s
->
iomem
);
if
(
chr
)
qemu_chr_add_handlers
(
chr
,
pxa2xx_fir_is_empty
,
...
...
@@ -2043,7 +2024,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
unsigned
int
sdram_size
,
const
char
*
revision
)
{
PXA2xxState
*
s
;
int
i
omemtype
,
i
;
int
i
;
DriveInfo
*
dinfo
;
s
=
(
PXA2xxState
*
)
g_malloc0
(
sizeof
(
PXA2xxState
));
...
...
@@ -2062,12 +2043,11 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
s
->
reset
=
qemu_allocate_irqs
(
pxa2xx_reset
,
s
,
1
)[
0
];
/* SDRAM & Internal Memory Storage */
cpu_register_physical_memory
(
PXA2XX_SDRAM_BASE
,
sdram_size
,
qemu_ram_alloc
(
NULL
,
"pxa270.sdram"
,
sdram_size
)
|
IO_MEM_RAM
);
cpu_register_physical_memory
(
PXA2XX_INTERNAL_BASE
,
0x40000
,
qemu_ram_alloc
(
NULL
,
"pxa270.internal"
,
0x40000
)
|
IO_MEM_RAM
);
memory_region_init_ram
(
&
s
->
sdram
,
NULL
,
"pxa270.sdram"
,
sdram_size
);
memory_region_add_subregion
(
address_space
,
PXA2XX_SDRAM_BASE
,
&
s
->
sdram
);
memory_region_init_ram
(
&
s
->
internal
,
NULL
,
"pxa270.internal"
,
0x40000
);
memory_region_add_subregion
(
address_space
,
PXA2XX_INTERNAL_BASE
,
&
s
->
internal
);
s
->
pic
=
pxa2xx_pic_init
(
0x40d00000
,
s
->
env
);
...
...
@@ -2105,7 +2085,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
}
}
if
(
serial_hds
[
i
])
s
->
fir
=
pxa2xx_fir_init
(
0x40800000
,
s
->
fir
=
pxa2xx_fir_init
(
address_space
,
0x40800000
,
qdev_get_gpio_in
(
s
->
pic
,
PXA2XX_PIC_ICP
),
qdev_get_gpio_in
(
s
->
dma
,
PXA2XX_RX_RQ_ICP
),
qdev_get_gpio_in
(
s
->
dma
,
PXA2XX_TX_RQ_ICP
),
...
...
@@ -2117,9 +2097,8 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
s
->
cm_base
=
0x41300000
;
s
->
cm_regs
[
CCCR
>>
2
]
=
0x02000210
;
/* 416.0 MHz */
s
->
clkcfg
=
0x00000009
;
/* Turbo mode active */
iomemtype
=
cpu_register_io_memory
(
pxa2xx_cm_readfn
,
pxa2xx_cm_writefn
,
s
,
DEVICE_NATIVE_ENDIAN
);
cpu_register_physical_memory
(
s
->
cm_base
,
0x1000
,
iomemtype
);
memory_region_init_io
(
&
s
->
cm_iomem
,
&
pxa2xx_cm_ops
,
s
,
"pxa2xx-cm"
,
0x1000
);
memory_region_add_subregion
(
address_space
,
s
->
cm_base
,
&
s
->
cm_iomem
);
vmstate_register
(
NULL
,
0
,
&
vmstate_pxa2xx_cm
,
s
);
cpu_arm_set_cp_io
(
s
->
env
,
14
,
pxa2xx_cp14_read
,
pxa2xx_cp14_write
,
s
);
...
...
@@ -2128,15 +2107,13 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
s
->
mm_regs
[
MDMRS
>>
2
]
=
0x00020002
;
s
->
mm_regs
[
MDREFR
>>
2
]
=
0x03ca4000
;
s
->
mm_regs
[
MECR
>>
2
]
=
0x00000001
;
/* Two PC Card sockets */
iomemtype
=
cpu_register_io_memory
(
pxa2xx_mm_readfn
,
pxa2xx_mm_writefn
,
s
,
DEVICE_NATIVE_ENDIAN
);
cpu_register_physical_memory
(
s
->
mm_base
,
0x1000
,
iomemtype
);
memory_region_init_io
(
&
s
->
mm_iomem
,
&
pxa2xx_mm_ops
,
s
,
"pxa2xx-mm"
,
0x1000
);
memory_region_add_subregion
(
address_space
,
s
->
mm_base
,
&
s
->
mm_iomem
);
vmstate_register
(
NULL
,
0
,
&
vmstate_pxa2xx_mm
,
s
);
s
->
pm_base
=
0x40f00000
;
iomemtype
=
cpu_register_io_memory
(
pxa2xx_pm_readfn
,
pxa2xx_pm_writefn
,
s
,
DEVICE_NATIVE_ENDIAN
);
cpu_register_physical_memory
(
s
->
pm_base
,
0x100
,
iomemtype
);
memory_region_init_io
(
&
s
->
pm_iomem
,
&
pxa2xx_pm_ops
,
s
,
"pxa2xx-pm"
,
0x100
);
memory_region_add_subregion
(
address_space
,
s
->
pm_base
,
&
s
->
pm_iomem
);
vmstate_register
(
NULL
,
0
,
&
vmstate_pxa2xx_pm
,
s
);
for
(
i
=
0
;
pxa27x_ssp
[
i
].
io_base
;
i
++
);
...
...
@@ -2182,7 +2159,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
PXA2xxState
*
pxa255_init
(
MemoryRegion
*
address_space
,
unsigned
int
sdram_size
)
{
PXA2xxState
*
s
;
int
i
omemtype
,
i
;
int
i
;
DriveInfo
*
dinfo
;
s
=
(
PXA2xxState
*
)
g_malloc0
(
sizeof
(
PXA2xxState
));
...
...
@@ -2195,12 +2172,12 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s
->
reset
=
qemu_allocate_irqs
(
pxa2xx_reset
,
s
,
1
)[
0
];
/* SDRAM & Internal Memory Storage */
cpu_register_physical_memory
(
PXA2XX_SDRAM_BASE
,
sdram_size
,
qemu_ram_alloc
(
NULL
,
"pxa255.sdram"
,
sdram_size
)
|
IO_MEM_RAM
);
cpu_register_physical_memory
(
PXA2XX_INTERNAL_BASE
,
PXA2XX_INTERNAL_SIZE
,
qemu_ram_alloc
(
NULL
,
"pxa255.internal"
,
PXA2XX_INTERNAL_SIZE
)
|
IO_MEM_RAM
);
memory_region_init_ram
(
&
s
->
sdram
,
NULL
,
"pxa255.sdram"
,
sdram_size
);
memory_region_add_subregion
(
address_space
,
PXA2XX_SDRAM_BASE
,
&
s
->
sdram
);
memory_region_init_ram
(
&
s
->
internal
,
NULL
,
"pxa255.internal"
,
PXA2XX_INTERNAL_SIZE
);
memory_region_add_subregion
(
address_space
,
PXA2XX_INTERNAL_BASE
,
&
s
->
internal
);
s
->
pic
=
pxa2xx_pic_init
(
0x40d00000
,
s
->
env
);
...
...
@@ -2237,7 +2214,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
}
}
if
(
serial_hds
[
i
])
s
->
fir
=
pxa2xx_fir_init
(
0x40800000
,
s
->
fir
=
pxa2xx_fir_init
(
address_space
,
0x40800000
,
qdev_get_gpio_in
(
s
->
pic
,
PXA2XX_PIC_ICP
),
qdev_get_gpio_in
(
s
->
dma
,
PXA2XX_RX_RQ_ICP
),
qdev_get_gpio_in
(
s
->
dma
,
PXA2XX_TX_RQ_ICP
),
...
...
@@ -2249,9 +2226,8 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s
->
cm_base
=
0x41300000
;
s
->
cm_regs
[
CCCR
>>
2
]
=
0x02000210
;
/* 416.0 MHz */
s
->
clkcfg
=
0x00000009
;
/* Turbo mode active */
iomemtype
=
cpu_register_io_memory
(
pxa2xx_cm_readfn
,
pxa2xx_cm_writefn
,
s
,
DEVICE_NATIVE_ENDIAN
);
cpu_register_physical_memory
(
s
->
cm_base
,
0x1000
,
iomemtype
);
memory_region_init_io
(
&
s
->
cm_iomem
,
&
pxa2xx_cm_ops
,
s
,
"pxa2xx-cm"
,
0x1000
);
memory_region_add_subregion
(
address_space
,
s
->
cm_base
,
&
s
->
cm_iomem
);
vmstate_register
(
NULL
,
0
,
&
vmstate_pxa2xx_cm
,
s
);
cpu_arm_set_cp_io
(
s
->
env
,
14
,
pxa2xx_cp14_read
,
pxa2xx_cp14_write
,
s
);
...
...
@@ -2260,15 +2236,13 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s
->
mm_regs
[
MDMRS
>>
2
]
=
0x00020002
;
s
->
mm_regs
[
MDREFR
>>
2
]
=
0x03ca4000
;
s
->
mm_regs
[
MECR
>>
2
]
=
0x00000001
;
/* Two PC Card sockets */
iomemtype
=
cpu_register_io_memory
(
pxa2xx_mm_readfn
,
pxa2xx_mm_writefn
,
s
,
DEVICE_NATIVE_ENDIAN
);
cpu_register_physical_memory
(
s
->
mm_base
,
0x1000
,
iomemtype
);
memory_region_init_io
(
&
s
->
mm_iomem
,
&
pxa2xx_mm_ops
,
s
,
"pxa2xx-mm"
,
0x1000
);
memory_region_add_subregion
(
address_space
,
s
->
mm_base
,
&
s
->
mm_iomem
);
vmstate_register
(
NULL
,
0
,
&
vmstate_pxa2xx_mm
,
s
);
s
->
pm_base
=
0x40f00000
;
iomemtype
=
cpu_register_io_memory
(
pxa2xx_pm_readfn
,
pxa2xx_pm_writefn
,
s
,
DEVICE_NATIVE_ENDIAN
);
cpu_register_physical_memory
(
s
->
pm_base
,
0x100
,
iomemtype
);
memory_region_init_io
(
&
s
->
pm_iomem
,
&
pxa2xx_pm_ops
,
s
,
"pxa2xx-pm"
,
0x100
);
memory_region_add_subregion
(
address_space
,
s
->
pm_base
,
&
s
->
pm_iomem
);
vmstate_register
(
NULL
,
0
,
&
vmstate_pxa2xx_pm
,
s
);
for
(
i
=
0
;
pxa255_ssp
[
i
].
io_base
;
i
++
);
...
...
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