From 9940a96bc8d29a385cd00b80e52124e931a379cd Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 19 Mar 2010 13:03:58 -0700 Subject: [PATCH] tcg: Allow target-specific implementation of NAND. Signed-off-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/mips/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/ppc64/tcg-target.h | 2 ++ tcg/s390/tcg-target.h | 2 ++ tcg/sparc/tcg-target.h | 2 ++ tcg/tcg-op.h | 11 +++++++++++ tcg/tcg-opc.h | 6 ++++++ tcg/x86_64/tcg-target.h | 2 ++ 10 files changed, 29 insertions(+) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index cfcd4af4a7..ba0d854aa5 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -68,6 +68,7 @@ enum { #define TCG_TARGET_HAS_andc_i32 // #define TCG_TARGET_HAS_orc_i32 // #define TCG_TARGET_HAS_eqv_i32 +// #define TCG_TARGET_HAS_nand_i32 #define TCG_TARGET_HAS_GUEST_BASE diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 83e004b620..7a2bdeb63a 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -58,6 +58,7 @@ enum { // #define TCG_TARGET_HAS_andc_i32 // #define TCG_TARGET_HAS_orc_i32 // #define TCG_TARGET_HAS_eqv_i32 +// #define TCG_TARGET_HAS_nand_i32 #define TCG_TARGET_HAS_GUEST_BASE diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 00f89f473b..7af2e70281 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -88,6 +88,7 @@ enum { #undef TCG_TARGET_HAS_andc_i32 #undef TCG_TARGET_HAS_orc_i32 #undef TCG_TARGET_HAS_eqv_i32 +#undef TCG_TARGET_HAS_nand_i32 /* optional instructions automatically implemented */ #undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */ diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index d0c4761347..1daa93d78c 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -90,6 +90,7 @@ enum { #define TCG_TARGET_HAS_andc_i32 #define TCG_TARGET_HAS_orc_i32 /* #define TCG_TARGET_HAS_eqv_i32 */ +/* #define TCG_TARGET_HAS_nand_i32 */ #define TCG_AREG0 TCG_REG_R27 diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index 11096c5163..8ddbd2fb2b 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -81,6 +81,7 @@ enum { /* #define TCG_TARGET_HAS_andc_i32 */ /* #define TCG_TARGET_HAS_orc_i32 */ /* #define TCG_TARGET_HAS_eqv_i32 */ +/* #define TCG_TARGET_HAS_nand_i32 */ #define TCG_TARGET_HAS_div_i64 /* #define TCG_TARGET_HAS_rot_i64 */ @@ -98,6 +99,7 @@ enum { /* #define TCG_TARGET_HAS_andc_i64 */ /* #define TCG_TARGET_HAS_orc_i64 */ /* #define TCG_TARGET_HAS_eqv_i64 */ +/* #define TCG_TARGET_HAS_nand_i64 */ #define TCG_AREG0 TCG_REG_R27 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 2d10e73b81..b96ce19fd1 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -60,6 +60,7 @@ enum { // #define TCG_TARGET_HAS_andc_i32 // #define TCG_TARGET_HAS_orc_i32 // #define TCG_TARGET_HAS_eqv_i32 +// #define TCG_TARGET_HAS_nand_i32 // #define TCG_TARGET_HAS_div_i64 // #define TCG_TARGET_HAS_rot_i64 @@ -77,6 +78,7 @@ enum { // #define TCG_TARGET_HAS_andc_i64 // #define TCG_TARGET_HAS_orc_i64 // #define TCG_TARGET_HAS_eqv_i64 +// #define TCG_TARGET_HAS_nand_i64 /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_R15 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index aabdd9dc50..c7d0b6a103 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -101,6 +101,7 @@ enum { #define TCG_TARGET_HAS_andc_i32 #define TCG_TARGET_HAS_orc_i32 // #define TCG_TARGET_HAS_eqv_i32 +// #define TCG_TARGET_HAS_nand_i32 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_div_i64 @@ -119,6 +120,7 @@ enum { #define TCG_TARGET_HAS_andc_i64 #define TCG_TARGET_HAS_orc_i64 // #define TCG_TARGET_HAS_eqv_i64 +// #define TCG_TARGET_HAS_nand_i64 #endif /* Note: must be synced with dyngen-exec.h */ diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index b535406363..d028f7f4e4 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1763,14 +1763,25 @@ static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { +#ifdef TCG_TARGET_HAS_nand_i32 + tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2); +#else tcg_gen_and_i32(ret, arg1, arg2); tcg_gen_not_i32(ret, ret); +#endif } static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { +#ifdef TCG_TARGET_HAS_nand_i64 + tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2); +#elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32 + tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +#else tcg_gen_and_i64(ret, arg1, arg2); tcg_gen_not_i64(ret, ret); +#endif } static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 8c34a83d27..a20d3d877a 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -119,6 +119,9 @@ DEF2(orc_i32, 1, 2, 0, 0) #ifdef TCG_TARGET_HAS_eqv_i32 DEF2(eqv_i32, 1, 2, 0, 0) #endif +#ifdef TCG_TARGET_HAS_nand_i32 +DEF2(nand_i32, 1, 2, 0, 0) +#endif #if TCG_TARGET_REG_BITS == 64 DEF2(mov_i64, 1, 1, 0, 0) @@ -205,6 +208,9 @@ DEF2(orc_i64, 1, 2, 0, 0) #ifdef TCG_TARGET_HAS_eqv_i64 DEF2(eqv_i64, 1, 2, 0, 0) #endif +#ifdef TCG_TARGET_HAS_nand_i64 +DEF2(nand_i64, 1, 2, 0, 0) +#endif #endif /* QEMU specific */ diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h index 2225faa625..e9905672b4 100644 --- a/tcg/x86_64/tcg-target.h +++ b/tcg/x86_64/tcg-target.h @@ -86,6 +86,8 @@ enum { // #define TCG_TARGET_HAS_orc_i64 // #define TCG_TARGET_HAS_eqv_i32 // #define TCG_TARGET_HAS_eqv_i64 +// #define TCG_TARGET_HAS_nand_i32 +// #define TCG_TARGET_HAS_nand_i64 #define TCG_TARGET_HAS_GUEST_BASE -- GitLab