target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 mode
Previous implementation presumed that FPU registers are 64-bit and are working in 64-bit mode. This change first checks MIPS_HFLAG_F64 and if not set, it does load/store from the odd numbered register pair. Patch by Matthew Fortune. Signed-off-by: NMatthew Fortune <matthew.fortune@imgtec.com> Signed-off-by: NPetar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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