From 662cefb7753c1f04d960b443c60e7622c83144d3 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 19 Aug 2014 18:56:26 +0100 Subject: [PATCH] target-arm: Correctly handle PSTATE.SS when taking exception to AArch32 When an exception is taken to AArch32, we must clear the PSTATE.SS bit for the exception handler, and must also ensure that the SS bit is not set in the value saved to SPSR_. Achieve both of these aims by clearing the bit in uncached_cpsr before saving it to the SPSR. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target-arm/helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 22bf6d3f68..f981569ae2 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3550,6 +3550,10 @@ void arm_cpu_do_interrupt(CPUState *cs) addr += env->cp15.vbar_el[1]; } switch_mode (env, new_mode); + /* For exceptions taken to AArch32 we must clear the SS bit in both + * PSTATE and in the old-state value we save to SPSR_, so zero it now. + */ + env->uncached_cpsr &= ~PSTATE_SS; env->spsr = cpsr_read(env); /* Clear IT bits. */ env->condexec_bits = 0; -- GitLab