From 5de56742a3c91de3d646326bec43a989bba83ca4 Mon Sep 17 00:00:00 2001 From: Amir Charif Date: Fri, 15 Mar 2019 11:12:29 +0000 Subject: [PATCH] target/arm: Check access permission to ADDVL/ADDPL/RDVL These instructions do not trap when SVE is disabled in EL0, causing them to be executed with wrong size information. Signed-off-by: Amir Charif Message-id: 1552579248-31025-1-git-send-email-amir.charif@cea.fr Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell [PMM: added 'target/arm' prefix to subject] Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 3a2eb51566..245cd82621 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -943,24 +943,30 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a) static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) { - TCGv_i64 rd = cpu_reg_sp(s, a->rd); - TCGv_i64 rn = cpu_reg_sp(s, a->rn); - tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s)); + if (sve_access_check(s)) { + TCGv_i64 rd = cpu_reg_sp(s, a->rd); + TCGv_i64 rn = cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s)); + } return true; } static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { - TCGv_i64 rd = cpu_reg_sp(s, a->rd); - TCGv_i64 rn = cpu_reg_sp(s, a->rn); - tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s)); + if (sve_access_check(s)) { + TCGv_i64 rd = cpu_reg_sp(s, a->rd); + TCGv_i64 rn = cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s)); + } return true; } static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { - TCGv_i64 reg = cpu_reg(s, a->rd); - tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); + if (sve_access_check(s)) { + TCGv_i64 reg = cpu_reg(s, a->rd); + tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s)); + } return true; } -- GitLab