提交 5c8556a6 编写于 作者: G Guan Xuetao 提交者: Blue Swirl

unicore32-softmmu: Add puv3 interrupt support

This patch adds puv3 interrupt support, include interrupt controler
device simulation and interrupt handler in puv3 machine.
Signed-off-by: NGuan Xuetao <gxt@mprc.pku.edu.cn>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
上级 fbbdf983
...@@ -66,6 +66,9 @@ hw-obj-$(CONFIG_XILINX) += xilinx_uartlite.o ...@@ -66,6 +66,9 @@ hw-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
# PKUnity SoC devices
hw-obj-$(CONFIG_PUV3) += puv3_intc.o
# PCI watchdog devices # PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
......
...@@ -22,9 +22,30 @@ ...@@ -22,9 +22,30 @@
#define KERNEL_LOAD_ADDR 0x03000000 #define KERNEL_LOAD_ADDR 0x03000000
#define KERNEL_MAX_SIZE 0x00800000 /* Just a guess */ #define KERNEL_MAX_SIZE 0x00800000 /* Just a guess */
static void puv3_intc_cpu_handler(void *opaque, int irq, int level)
{
CPUUniCore32State *env = opaque;
assert(irq == 0);
if (level) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
}
static void puv3_soc_init(CPUUniCore32State *env) static void puv3_soc_init(CPUUniCore32State *env)
{ {
/* TODO */ qemu_irq *cpu_intc, irqs[PUV3_IRQS_NR];
DeviceState *dev;
int i;
/* Initialize interrupt controller */
cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler, env, 1);
dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, *cpu_intc);
for (i = 0; i < PUV3_IRQS_NR; i++) {
irqs[i] = qdev_get_gpio_in(dev, i);
}
} }
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size) static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
......
/*
* INTC device simulation in PKUnity SoC
*
* Copyright (C) 2010-2012 Guan Xuetao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation, or any later version.
* See the COPYING file in the top-level directory.
*/
#include "sysbus.h"
#undef DEBUG_PUV3
#include "puv3.h"
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq parent_irq;
uint32_t reg_ICMR;
uint32_t reg_ICPR;
} PUV3INTCState;
/* Update interrupt status after enabled or pending bits have been changed. */
static void puv3_intc_update(PUV3INTCState *s)
{
if (s->reg_ICMR & s->reg_ICPR) {
qemu_irq_raise(s->parent_irq);
} else {
qemu_irq_lower(s->parent_irq);
}
}
/* Process a change in an external INTC input. */
static void puv3_intc_handler(void *opaque, int irq, int level)
{
PUV3INTCState *s = opaque;
DPRINTF("irq 0x%x, level 0x%x\n", irq, level);
if (level) {
s->reg_ICPR |= (1 << irq);
} else {
s->reg_ICPR &= ~(1 << irq);
}
puv3_intc_update(s);
}
static uint64_t puv3_intc_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
PUV3INTCState *s = opaque;
uint32_t ret = 0;
switch (offset) {
case 0x04: /* INTC_ICMR */
ret = s->reg_ICMR;
break;
case 0x0c: /* INTC_ICIP */
ret = s->reg_ICPR; /* the same value with ICPR */
break;
default:
DPRINTF("Bad offset %x\n", (int)offset);
}
DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
return ret;
}
static void puv3_intc_write(void *opaque, target_phys_addr_t offset,
uint64_t value, unsigned size)
{
PUV3INTCState *s = opaque;
DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
switch (offset) {
case 0x00: /* INTC_ICLR */
case 0x14: /* INTC_ICCR */
break;
case 0x04: /* INTC_ICMR */
s->reg_ICMR = value;
break;
default:
DPRINTF("Bad offset 0x%x\n", (int)offset);
return;
}
puv3_intc_update(s);
}
static const MemoryRegionOps puv3_intc_ops = {
.read = puv3_intc_read,
.write = puv3_intc_write,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int puv3_intc_init(SysBusDevice *dev)
{
PUV3INTCState *s = FROM_SYSBUS(PUV3INTCState, dev);
qdev_init_gpio_in(&s->busdev.qdev, puv3_intc_handler, PUV3_IRQS_NR);
sysbus_init_irq(&s->busdev, &s->parent_irq);
s->reg_ICMR = 0;
s->reg_ICPR = 0;
memory_region_init_io(&s->iomem, &puv3_intc_ops, s, "puv3_intc",
PUV3_REGS_OFFSET);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static void puv3_intc_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
sdc->init = puv3_intc_init;
}
static const TypeInfo puv3_intc_info = {
.name = "puv3_intc",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PUV3INTCState),
.class_init = puv3_intc_class_init,
};
static void puv3_intc_register_type(void)
{
type_register_static(&puv3_intc_info);
}
type_init(puv3_intc_register_type)
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