Skip to content

Q
qemu

openeuler / qemu

通知 10
Star 0
Fork 0
Q
qemu

体验新版 GitCode，发现更多精彩内容 >>

提交 46f42f29 编写于 作者: B blueswir1
浏览文件
操作

Update from binutils 2.17 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5543 c046a42c-6fe2-441c-8c8c-71466251a162
上级 d4abd567
显示空白变更内容
内联 并排
Showing with 627 addition and 579 deletion
sparc-dis.c
浏览文件 @ 46f42f29
......@@ -5,23 +5,28 @@
/* include/opcode/sparc.h */
/* Print SPARC instructions.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2002 Free Software Foundation, Inc.
/* Definitions for opcode table for the sparc.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
2003, 2005 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
the GNU Binutils.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <stdlib.h>
#include "dis-asm.h"
......@@ -40,17 +45,18 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
Don't change this without updating sparc-opc.c. */
enum sparc_opcode_arch_val {
enum sparc_opcode_arch_val
{
SPARC_OPCODE_ARCH_V6 = 0,
SPARC_OPCODE_ARCH_V7,
SPARC_OPCODE_ARCH_V8,
SPARC_OPCODE_ARCH_SPARCLET,
SPARC_OPCODE_ARCH_SPARCLITE,
/* v9 variants must appear last */
/* V9 variants must appear last. */
SPARC_OPCODE_ARCH_V9,
SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
};
/* The highest architecture in the table. */
......@@ -65,14 +71,15 @@ enum sparc_opcode_arch_val {
/* Table of cpu variants. */
struct sparc_opcode_arch {
typedef struct sparc_opcode_arch
{
const char *name;
/* Mask of sparc_opcode_arch_val's supported.
EG: For v7 this would be
(SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
These are short's because sparc_opcode.architecture is. */
short supported;
};
} sparc_opcode_arch;
static const struct sparc_opcode_arch sparc_opcode_archs[];
......@@ -82,14 +89,15 @@ static const struct sparc_opcode_arch sparc_opcode_archs[];
/* Non-zero if ARCH1 conflicts with ARCH2.
IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
!= SPARC_OPCODE_SUPPORTED (ARCH1)) \
&& ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
!= SPARC_OPCODE_SUPPORTED (ARCH2)))
/* Structure of an opcode table entry. */
struct sparc_opcode {
typedef struct sparc_opcode
{
const char *name;
unsigned long match; /* Bits that must be set. */
unsigned long lose; /* Bits that must not be set. */
......@@ -97,29 +105,27 @@ struct sparc_opcode {
/* This was called "delayed" in versions before the flags. */
char flags;
short architecture; /* Bitmask of sparc_opcode_arch_val's. */
};
#define F_DELAYED 1 /* Delayed branch */
#define F_ALIAS 2 /* Alias for a "real" instruction */
#define F_UNBR 4 /* Unconditional branch */
#define F_CONDBR 8 /* Conditional branch */
#define F_JSR 16 /* Subroutine call */
#define F_FLOAT 32 /* Floating point instruction (not a branch) */
#define F_FBR 64 /* Floating point branch */
} sparc_opcode;
#define F_DELAYED 1 /* Delayed branch. */
#define F_ALIAS 2 /* Alias for a "real" instruction. */
#define F_UNBR 4 /* Unconditional branch. */
#define F_CONDBR 8 /* Conditional branch. */
#define F_JSR 16 /* Subroutine call. */
#define F_FLOAT 32 /* Floating point instruction (not a branch). */
#define F_FBR 64 /* Floating point branch. */
/* FIXME: Add F_ANACHRONISTIC flag for v9. */
/*
All sparc opcodes are 32 bits, except for the `set' instruction (really a
macro), which is 64 bits. It is handled as a special case.
/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
macro), which is 64 bits. It is handled as a special case.
The match component is a mask saying which bits must match a particular
opcode in order for an instruction to be an instance of that opcode.
The match component is a mask saying which bits must match a particular
opcode in order for an instruction to be an instance of that opcode.
The args component is a string containing one character for each operand of the
instruction.
The args component is a string containing one character for each operand of the
instruction.
Kinds of operands:
Kinds of operands:
# Number used by optimizer. It is ignored.
1 rs1 register.
2 rs2 register.
......@@ -187,49 +193,78 @@ Kinds of operands:
_ Ancillary state register in rd (v9a)
/ Ancillary state register in rs1 (v9a)
The following chars are unused: (note: ,[] are used as punctuation)
[45]
*/
#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */
#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */
#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */
#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */
#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */
#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */
#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */
#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
#define F1(x) (OP(x))
#define DISP30(x) ((x)&0x3fffffff)
#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */
#define RS2(x) ((x)&0x1f) /* rs2 field */
#define SIMM13(x) ((x)&0x1fff) /* simm13 field */
#define RD(x) (((x)&0x1f) << 25) /* destination register field */
#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
#define ASI_RS2(x) (SIMM13(x))
#define MEMBAR(x) ((x)&0x7f)
#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */
#define ANNUL (1<<29)
#define BPRED (1<<19) /* v9 */
#define IMMED F3I(1)
#define RD_G0 RD(~0)
#define RS1_G0 RS1(~0)
#define RS2_G0 RS2(~0)
The following chars are unused: (note: ,[] are used as punctuation)
[45]. */
#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
#define F1(x) (OP (x))
#define DISP30(x) ((x) & 0x3fffffff)
#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
#define ASI_RS2(x) (SIMM13 (x))
#define MEMBAR(x) ((x) & 0x7f)
#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
#define ANNUL (1 << 29)
#define BPRED (1 << 19) /* V9. */
#define IMMED F3I (1)
#define RD_G0 RD (~0)
#define RS1_G0 RS1 (~0)
#define RS2_G0 RS2 (~0)
static const struct sparc_opcode sparc_opcodes[];
static const int sparc_num_opcodes;
static const char *sparc_decode_asi_v8 PARAMS ((int));
static const char *sparc_decode_asi_v9 PARAMS ((int));
static const char *sparc_decode_membar PARAMS ((int));
static const char *sparc_decode_prefetch PARAMS ((int));
static const char *sparc_decode_sparclet_cpreg PARAMS ((int));
static const char *sparc_decode_asi_v8 (int);
static const char *sparc_decode_asi_v9 (int);
static const char *sparc_decode_membar (int);
static const char *sparc_decode_prefetch (int);
static const char *sparc_decode_sparclet_cpreg (int);
/* Local Variables:
fill-column: 131
comment-column: 0
End: */
/* opcodes/sparc-opc.c */
/* Table of opcodes for the sparc.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2002, 2004, 2005
Free Software Foundation, Inc.
This file is part of the BFD library.
BFD is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2, or (at your option) any later
version.
BFD is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with this software; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
/* FIXME-someday: perhaps the ,a's and such should be embedded in the
instruction's name rather than the args. This would make gas faster, pinsn
slower, but would mess up some macros a bit. xoxorich. */
/* Some defines to make life easy. */
#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
......@@ -244,7 +279,7 @@ static const char *sparc_decode_sparclet_cpreg PARAMS ((int));
#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
/* v6 insns not supported on the sparclet */
/* v6 insns not supported on the sparclet. */
#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
......@@ -262,17 +297,18 @@ static const char *sparc_decode_sparclet_cpreg PARAMS ((int));
#define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
#define v9a (MASK_V9A | MASK_V9B)
#define v9b (MASK_V9B)
/* v6 insns not supported by v9 */
/* v6 insns not supported by v9. */
#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
| MASK_SPARCLET | MASK_SPARCLITE)
/* v9a instructions which would appear to be aliases to v9's impdep's
otherwise */
otherwise. */
#define v9notv9a (MASK_V9)
/* Table of opcode architectures.
The order is defined in opcode/sparc.h. */
static const struct sparc_opcode_arch sparc_opcode_archs[] = {
static const struct sparc_opcode_arch sparc_opcode_archs[] =
{
{ "v6", MASK_V6 },
{ "v7", MASK_V6 | MASK_V7 },
{ "v8", MASK_V6 | MASK_V7 | MASK_V8 },
......@@ -288,69 +324,67 @@ static const struct sparc_opcode_arch sparc_opcode_archs[] = {
};
/* Branch condition field. */
#define COND(x) (((x)&0xf)<<25)
#define COND(x) (((x) & 0xf) << 25)
/* v9: Move (MOVcc and FMOVcc) condition field. */
#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */
#define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
/* v9: Move register (MOVRcc and FMOVRcc) condition field. */
#define RCOND(x) (((x)&0x7)<<10) /* v9 */
#define CONDA (COND(0x8))
#define CONDCC (COND(0xd))
#define CONDCS (COND(0x5))
#define CONDE (COND(0x1))
#define CONDG (COND(0xa))
#define CONDGE (COND(0xb))
#define CONDGU (COND(0xc))
#define CONDL (COND(0x3))
#define CONDLE (COND(0x2))
#define CONDLEU (COND(0x4))
#define CONDN (COND(0x0))
#define CONDNE (COND(0x9))
#define CONDNEG (COND(0x6))
#define CONDPOS (COND(0xe))
#define CONDVC (COND(0xf))
#define CONDVS (COND(0x7))
#define RCOND(x) (((x) & 0x7) << 10) /* v9 */
#define CONDA (COND (0x8))
#define CONDCC (COND (0xd))
#define CONDCS (COND (0x5))
#define CONDE (COND (0x1))
#define CONDG (COND (0xa))
#define CONDGE (COND (0xb))
#define CONDGU (COND (0xc))
#define CONDL (COND (0x3))
#define CONDLE (COND (0x2))
#define CONDLEU (COND (0x4))
#define CONDN (COND (0x0))
#define CONDNE (COND (0x9))
#define CONDNEG (COND (0x6))
#define CONDPOS (COND (0xe))
#define CONDVC (COND (0xf))
#define CONDVS (COND (0x7))
#define CONDNZ CONDNE
#define CONDZ CONDE
#define CONDGEU CONDCC
#define CONDLU CONDCS
#define FCONDA (COND(0x8))
#define FCONDE (COND(0x9))
#define FCONDG (COND(0x6))
#define FCONDGE (COND(0xb))
#define FCONDL (COND(0x4))
#define FCONDLE (COND(0xd))
#define FCONDLG (COND(0x2))
#define FCONDN (COND(0x0))
#define FCONDNE (COND(0x1))
#define FCONDO (COND(0xf))
#define FCONDU (COND(0x7))
#define FCONDUE (COND(0xa))
#define FCONDUG (COND(0x5))
#define FCONDUGE (COND(0xc))
#define FCONDUL (COND(0x3))
#define FCONDULE (COND(0xe))
#define FCONDA (COND (0x8))
#define FCONDE (COND (0x9))
#define FCONDG (COND (0x6))
#define FCONDGE (COND (0xb))
#define FCONDL (COND (0x4))
#define FCONDLE (COND (0xd))
#define FCONDLG (COND (0x2))
#define FCONDN (COND (0x0))
#define FCONDNE (COND (0x1))
#define FCONDO (COND (0xf))
#define FCONDU (COND (0x7))
#define FCONDUE (COND (0xa))
#define FCONDUG (COND (0x5))
#define FCONDUGE (COND (0xc))
#define FCONDUL (COND (0x3))
#define FCONDULE (COND (0xe))
#define FCONDNZ FCONDNE
#define FCONDZ FCONDE
#define ICC (0) /* v9 */
#define XCC (1<<12) /* v9 */
#define FCC(x) (((x)&0x3)<<11) /* v9 */
#define FBFCC(x) (((x)&0x3)<<20) /* v9 */
#define XCC (1 << 12) /* v9 */
#define FCC(x) (((x) & 0x3) << 11) /* v9 */
#define FBFCC(x) (((x) & 0x3) << 20) /* v9 */
/* The order of the opcodes in the table is significant:
* The assembler requires that all instances of the same mnemonic must
be consecutive. If they aren't, the assembler will bomb at runtime.
* The disassembler should not care about the order of the opcodes.
*/
* The disassembler should not care about the order of the opcodes. */
/* Entries for commutative arithmetic operations. */
/* ??? More entries can make use of this. */
......@@ -881,6 +915,10 @@ static const struct sparc_opcode sparc_opcodes[] = {
{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
{ "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, v9 },
{ "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, v9 },
{ "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, v9 },
{ "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, v9 },
{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 },
{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 },
......@@ -1067,6 +1105,13 @@ static const struct sparc_opcode sparc_opcodes[] = {
{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */
{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */
{ "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, v9 }, /* rdhpr %hpriv,r */
{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, v9 }, /* wrhpr r1,r2,%hpriv */
{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, v9 }, /* wrhpr r1,%hpriv */
{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, v9 }, /* wrhpr r1,i,%hpriv */
{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS, v9 }, /* wrhpr i,r1,%hpriv */
{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, v9 }, /* wrhpr i,%hpriv */
/* ??? This group seems wrong. A three operand move? */
{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
......@@ -1458,110 +1503,72 @@ cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
#define FM_DF 2 /* v9 */
#define FM_QF 3 /* v9 */
#define fmovicc(opcode, fpsize, cond, flags) /* v9 */ \
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags, v9 }, \
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags, v9 }
#define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, v9 }, \
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, v9 }
#define fmovfcc(opcode, fpsize, fcond, flags) /* v9 */ \
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags, v9 }, \
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags, v9 }, \
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags, v9 }, \
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags, v9 }
#define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 }
/* FIXME: use fmovicc/fmovfcc? */ /* v9 */
#define fmovcc(opcode, fpsize, cond, fcond, flags) /* v9 */ \
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z,f,g", flags | F_FLOAT, v9 }, \
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6,f,g", flags | F_FLOAT, v9 }, \
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z,f,g", flags | F_FLOAT, v9 }, \
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7,f,g", flags | F_FLOAT, v9 }, \
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8,f,g", flags | F_FLOAT, v9 }, \
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9,f,g", flags | F_FLOAT, v9 }
/* v9 */ fmovcc ("fmovda", FM_DF, CONDA, FCONDA, 0),
/* v9 */ fmovcc ("fmovqa", FM_QF, CONDA, FCONDA, 0),
/* v9 */ fmovcc ("fmovsa", FM_SF, CONDA, FCONDA, 0),
/* v9 */ fmovicc ("fmovdcc", FM_DF, CONDCC, 0),
/* v9 */ fmovicc ("fmovqcc", FM_QF, CONDCC, 0),
/* v9 */ fmovicc ("fmovscc", FM_SF, CONDCC, 0),
/* v9 */ fmovicc ("fmovdcs", FM_DF, CONDCS, 0),
/* v9 */ fmovicc ("fmovqcs", FM_QF, CONDCS, 0),
/* v9 */ fmovicc ("fmovscs", FM_SF, CONDCS, 0),
/* v9 */ fmovcc ("fmovde", FM_DF, CONDE, FCONDE, 0),
/* v9 */ fmovcc ("fmovqe", FM_QF, CONDE, FCONDE, 0),
/* v9 */ fmovcc ("fmovse", FM_SF, CONDE, FCONDE, 0),
/* v9 */ fmovcc ("fmovdg", FM_DF, CONDG, FCONDG, 0),
/* v9 */ fmovcc ("fmovqg", FM_QF, CONDG, FCONDG, 0),
/* v9 */ fmovcc ("fmovsg", FM_SF, CONDG, FCONDG, 0),
/* v9 */ fmovcc ("fmovdge", FM_DF, CONDGE, FCONDGE, 0),
/* v9 */ fmovcc ("fmovqge", FM_QF, CONDGE, FCONDGE, 0),
/* v9 */ fmovcc ("fmovsge", FM_SF, CONDGE, FCONDGE, 0),
/* v9 */ fmovicc ("fmovdgeu", FM_DF, CONDGEU, F_ALIAS),
/* v9 */ fmovicc ("fmovqgeu", FM_QF, CONDGEU, F_ALIAS),
/* v9 */ fmovicc ("fmovsgeu", FM_SF, CONDGEU, F_ALIAS),
/* v9 */ fmovicc ("fmovdgu", FM_DF, CONDGU, 0),
/* v9 */ fmovicc ("fmovqgu", FM_QF, CONDGU, 0),
/* v9 */ fmovicc ("fmovsgu", FM_SF, CONDGU, 0),
/* v9 */ fmovcc ("fmovdl", FM_DF, CONDL, FCONDL, 0),
/* v9 */ fmovcc ("fmovql", FM_QF, CONDL, FCONDL, 0),
/* v9 */ fmovcc ("fmovsl", FM_SF, CONDL, FCONDL, 0),
/* v9 */ fmovcc ("fmovdle", FM_DF, CONDLE, FCONDLE, 0),
/* v9 */ fmovcc ("fmovqle", FM_QF, CONDLE, FCONDLE, 0),
/* v9 */ fmovcc ("fmovsle", FM_SF, CONDLE, FCONDLE, 0),
/* v9 */ fmovicc ("fmovdleu", FM_DF, CONDLEU, 0),
/* v9 */ fmovicc ("fmovqleu", FM_QF, CONDLEU, 0),
/* v9 */ fmovicc ("fmovsleu", FM_SF, CONDLEU, 0),
/* v9 */ fmovfcc ("fmovdlg", FM_DF, FCONDLG, 0),
/* v9 */ fmovfcc ("fmovqlg", FM_QF, FCONDLG, 0),
/* v9 */ fmovfcc ("fmovslg", FM_SF, FCONDLG, 0),
/* v9 */ fmovicc ("fmovdlu", FM_DF, CONDLU, F_ALIAS),
/* v9 */ fmovicc ("fmovqlu", FM_QF, CONDLU, F_ALIAS),
/* v9 */ fmovicc ("fmovslu", FM_SF, CONDLU, F_ALIAS),
/* v9 */ fmovcc ("fmovdn", FM_DF, CONDN, FCONDN, 0),
/* v9 */ fmovcc ("fmovqn", FM_QF, CONDN, FCONDN, 0),
/* v9 */ fmovcc ("fmovsn", FM_SF, CONDN, FCONDN, 0),
/* v9 */ fmovcc ("fmovdne", FM_DF, CONDNE, FCONDNE, 0),
/* v9 */ fmovcc ("fmovqne", FM_QF, CONDNE, FCONDNE, 0),
/* v9 */ fmovcc ("fmovsne", FM_SF, CONDNE, FCONDNE, 0),
/* v9 */ fmovicc ("fmovdneg", FM_DF, CONDNEG, 0),
/* v9 */ fmovicc ("fmovqneg", FM_QF, CONDNEG, 0),
/* v9 */ fmovicc ("fmovsneg", FM_SF, CONDNEG, 0),
/* v9 */ fmovcc ("fmovdnz", FM_DF, CONDNZ, FCONDNZ, F_ALIAS),
/* v9 */ fmovcc ("fmovqnz", FM_QF, CONDNZ, FCONDNZ, F_ALIAS),
/* v9 */ fmovcc ("fmovsnz", FM_SF, CONDNZ, FCONDNZ, F_ALIAS),
/* v9 */ fmovfcc ("fmovdo", FM_DF, FCONDO, 0),
/* v9 */ fmovfcc ("fmovqo", FM_QF, FCONDO, 0),
/* v9 */ fmovfcc ("fmovso", FM_SF, FCONDO, 0),
/* v9 */ fmovicc ("fmovdpos", FM_DF, CONDPOS, 0),
/* v9 */ fmovicc ("fmovqpos", FM_QF, CONDPOS, 0),
/* v9 */ fmovicc ("fmovspos", FM_SF, CONDPOS, 0),
/* v9 */ fmovfcc ("fmovdu", FM_DF, FCONDU, 0),
/* v9 */ fmovfcc ("fmovqu", FM_QF, FCONDU, 0),
/* v9 */ fmovfcc ("fmovsu", FM_SF, FCONDU, 0),
/* v9 */ fmovfcc ("fmovdue", FM_DF, FCONDUE, 0),
/* v9 */ fmovfcc ("fmovque", FM_QF, FCONDUE, 0),
/* v9 */ fmovfcc ("fmovsue", FM_SF, FCONDUE, 0),
/* v9 */ fmovfcc ("fmovdug", FM_DF, FCONDUG, 0),
/* v9 */ fmovfcc ("fmovqug", FM_QF, FCONDUG, 0),
/* v9 */ fmovfcc ("fmovsug", FM_SF, FCONDUG, 0),
/* v9 */ fmovfcc ("fmovduge", FM_DF, FCONDUGE, 0),
/* v9 */ fmovfcc ("fmovquge", FM_QF, FCONDUGE, 0),
/* v9 */ fmovfcc ("fmovsuge", FM_SF, FCONDUGE, 0),
/* v9 */ fmovfcc ("fmovdul", FM_DF, FCONDUL, 0),
/* v9 */ fmovfcc ("fmovqul", FM_QF, FCONDUL, 0),
/* v9 */ fmovfcc ("fmovsul", FM_SF, FCONDUL, 0),
/* v9 */ fmovfcc ("fmovdule", FM_DF, FCONDULE, 0),
/* v9 */ fmovfcc ("fmovqule", FM_QF, FCONDULE, 0),
/* v9 */ fmovfcc ("fmovsule", FM_SF, FCONDULE, 0),
/* v9 */ fmovicc ("fmovdvc", FM_DF, CONDVC, 0),
/* v9 */ fmovicc ("fmovqvc", FM_QF, CONDVC, 0),
/* v9 */ fmovicc ("fmovsvc", FM_SF, CONDVC, 0),
/* v9 */ fmovicc ("fmovdvs", FM_DF, CONDVS, 0),
/* v9 */ fmovicc ("fmovqvs", FM_QF, CONDVS, 0),
/* v9 */ fmovicc ("fmovsvs", FM_SF, CONDVS, 0),
/* v9 */ fmovcc ("fmovdz", FM_DF, CONDZ, FCONDZ, F_ALIAS),
/* v9 */ fmovcc ("fmovqz", FM_QF, CONDZ, FCONDZ, F_ALIAS),
/* v9 */ fmovcc ("fmovsz", FM_SF, CONDZ, FCONDZ, F_ALIAS),
#define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, v9 }, \
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, v9 }, \
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 }
#define fmovicc(suffix, cond, flags) /* v9 */ \
fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \
fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \
fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
#define fmovfcc(suffix, fcond, flags) /* v9 */ \
fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \
fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \
fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
#define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \
fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \
fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
/* v9 */ fmovcc ("a", CONDA, FCONDA, 0),
/* v9 */ fmovicc ("cc", CONDCC, 0),
/* v9 */ fmovicc ("cs", CONDCS, 0),
/* v9 */ fmovcc ("e", CONDE, FCONDE, 0),
/* v9 */ fmovcc ("g", CONDG, FCONDG, 0),
/* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0),
/* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS),
/* v9 */ fmovicc ("gu", CONDGU, 0),
/* v9 */ fmovcc ("l", CONDL, FCONDL, 0),
/* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0),
/* v9 */ fmovicc ("leu", CONDLEU, 0),
/* v9 */ fmovfcc ("lg", FCONDLG, 0),
/* v9 */ fmovicc ("lu", CONDLU, F_ALIAS),
/* v9 */ fmovcc ("n", CONDN, FCONDN, 0),
/* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0),
/* v9 */ fmovicc ("neg", CONDNEG, 0),
/* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS),
/* v9 */ fmovfcc ("o", FCONDO, 0),
/* v9 */ fmovicc ("pos", CONDPOS, 0),
/* v9 */ fmovfcc ("u", FCONDU, 0),
/* v9 */ fmovfcc ("ue", FCONDUE, 0),
/* v9 */ fmovfcc ("ug", FCONDUG, 0),
/* v9 */ fmovfcc ("uge", FCONDUGE, 0),
/* v9 */ fmovfcc ("ul", FCONDUL, 0),
/* v9 */ fmovfcc ("ule", FCONDULE, 0),
/* v9 */ fmovicc ("vc", CONDVC, 0),
/* v9 */ fmovicc ("vs", CONDVS, 0),
/* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS),
#undef fmoviccx /* v9 */
#undef fmovfccx /* v9 */
#undef fmovccx /* v9 */
#undef fmovicc /* v9 */
#undef fmovfcc /* v9 */
#undef fmovcc /* v9 */
......@@ -1571,13 +1578,13 @@ cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
/* Coprocessor branches. */
#define CBR(opcode, mask, lose, flags, arch) \
{ opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \
{ opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch }
{ opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, arch }, \
{ opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch }
/* Floating point branches. */
#define FBR(opcode, mask, lose, flags) \
{ opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED|F_FBR, v6 }, \
{ opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 }
{ opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, v6 }, \
{ opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 }
/* V9 extended floating point branches. */
#define FBRX(opcode, mask, lose, flags) /* v9 */ \
......@@ -1710,17 +1717,17 @@ CONDFC ("fbule", "cb013", 0xe, F_CONDBR),
{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 },
{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 },
{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 },
{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 },
{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 },
{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 },
{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 },
{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 },
{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 },
{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 },
{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 },
{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 },
{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 },
{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 },
{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 },
{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 },
{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 },
{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 },
......@@ -2050,16 +2057,10 @@ typedef struct
const char *name;
} arg;
/* Look up NAME in TABLE. */
static const char *lookup_value PARAMS ((const arg *, int));
/* Look up VALUE in TABLE. */
static const char *
lookup_value (table, value)
const arg *table;
int value;
lookup_value (const arg *table, int value)
{
const arg *p;
......@@ -2067,7 +2068,7 @@ lookup_value (table, value)
if (value == p->value)
return p->name;
return (char *) 0;
return NULL;
}
/* Handle ASI's. */
......@@ -2191,8 +2192,7 @@ static const arg membar_table[] =
/* Return the name for membar value VALUE or NULL if not found. */
static const char *
sparc_decode_membar (value)
int value;
sparc_decode_membar (int value)
{
return lookup_value (membar_table, value);
}
......@@ -2213,8 +2213,7 @@ static const arg prefetch_table[] =
/* Return the name for prefetch value VALUE or NULL if not found. */
static const char *
sparc_decode_prefetch (value)
int value;
sparc_decode_prefetch (int value)
{
return lookup_value (prefetch_table, value);
}
......@@ -2236,8 +2235,7 @@ static const arg sparclet_cpreg_table[] =
/* Return the name for sparclet cpreg value VALUE or NULL if not found. */
static const char *
sparc_decode_sparclet_cpreg (value)
int value;
sparc_decode_sparclet_cpreg (int value)
{
return lookup_value (sparclet_cpreg_table, value);
}
......@@ -2246,6 +2244,25 @@ sparc_decode_sparclet_cpreg (value)
/* opcodes/sparc-dis.c */
/* Print SPARC instructions.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* Bitmask of v9 architectures. */
#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
| (1 << SPARC_OPCODE_ARCH_V9A) \
......@@ -2256,7 +2273,7 @@ sparc_decode_sparclet_cpreg (value)
#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
/* The sorted opcode table. */
static const struct sparc_opcode **sorted_opcodes;
static const sparc_opcode **sorted_opcodes;
/* For faster lookup, after insns are sorted they are hashed. */
/* ??? I think there is room for even more improvement. */
......@@ -2268,17 +2285,13 @@ static const struct sparc_opcode **sorted_opcodes;
static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
#define HASH_INSN(INSN) \
((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
struct opcode_hash {
struct opcode_hash *next;
const struct sparc_opcode *opcode;
};
static struct opcode_hash *opcode_hash_table[HASH_SIZE];
typedef struct sparc_opcode_hash
{
struct sparc_opcode_hash *next;
const sparc_opcode *opcode;
} sparc_opcode_hash;
static void build_hash_table
PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int));
static int is_delayed_branch PARAMS ((unsigned long));
static int compare_opcodes PARAMS ((const void *, const void *));
static int compute_arch_mask PARAMS ((unsigned long));
static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
/* Sign-extend a value which is N bits long. */
#define SEX(value, bits) \
......@@ -2310,10 +2323,21 @@ static const char * const v9_priv_reg_names[] =
{
"tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
"wstate", "fq"
"wstate", "fq", "gl"
/* "ver" - special cased */
};
/* These are ordered according to there register number in
rdhpr and wrhpr insns. */
static const char * const v9_hpriv_reg_names[] =
{
"hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
"resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
"resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
"resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
"resv28", "resv29", "resv30", "hstick_cmpr"
};
/* These are ordered according to there register number in
rd and wr insns (-16). */
static const char * const v9a_asr_reg_names[] =
......@@ -2397,23 +2421,22 @@ static const char * const v9a_asr_reg_names[] =
unsigned int adisp30:30;
#define disp30 call.adisp30
} call;
};
*/
}; */
/* Nonzero if INSN is the opcode for a delayed branch. */
static int
is_delayed_branch (insn)
unsigned long insn;
is_delayed_branch (unsigned long insn)
{
struct opcode_hash *op;
sparc_opcode_hash *op;
for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
{
const struct sparc_opcode *opcode = op->opcode;
const sparc_opcode *opcode = op->opcode;
if ((opcode->match & insn) == opcode->match
&& (opcode->lose & insn) == 0)
return (opcode->flags & F_DELAYED);
return opcode->flags & F_DELAYED;
}
return 0;
}
......@@ -2424,6 +2447,236 @@ is_delayed_branch (insn)
to compare_opcodes. */
static unsigned int current_arch_mask;
/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
static int
compute_arch_mask (unsigned long mach)
{
switch (mach)
{
case 0 :
case bfd_mach_sparc :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
case bfd_mach_sparc_sparclet :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
case bfd_mach_sparc_sparclite :
case bfd_mach_sparc_sparclite_le :
/* sparclites insns are recognized by default (because that's how
they've always been treated, for better or worse). Kludge this by
indicating generic v8 is also selected. */
return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
| SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
case bfd_mach_sparc_v8plus :
case bfd_mach_sparc_v9 :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
case bfd_mach_sparc_v8plusa :
case bfd_mach_sparc_v9a :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
case bfd_mach_sparc_v8plusb :
case bfd_mach_sparc_v9b :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
}
abort ();
}
/* Compare opcodes A and B. */
static int
compare_opcodes (const void * a, const void * b)
{
sparc_opcode *op0 = * (sparc_opcode **) a;
sparc_opcode *op1 = * (sparc_opcode **) b;
unsigned long int match0 = op0->match, match1 = op1->match;
unsigned long int lose0 = op0->lose, lose1 = op1->lose;
register unsigned int i;
/* If one (and only one) insn isn't supported by the current architecture,
prefer the one that is. If neither are supported, but they're both for
the same architecture, continue processing. Otherwise (both unsupported
and for different architectures), prefer lower numbered arch's (fudged
by comparing the bitmasks). */
if (op0->architecture & current_arch_mask)
{
if (! (op1->architecture & current_arch_mask))
return -1;
}
else
{
if (op1->architecture & current_arch_mask)
return 1;
else if (op0->architecture != op1->architecture)
return op0->architecture - op1->architecture;
}
/* If a bit is set in both match and lose, there is something
wrong with the opcode table. */
if (match0 & lose0)
{
fprintf
(stderr,
/* xgettext:c-format */
_("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
op0->name, match0, lose0);
op0->lose &= ~op0->match;
lose0 = op0->lose;
}
if (match1 & lose1)
{
fprintf
(stderr,
/* xgettext:c-format */
_("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
op1->name, match1, lose1);
op1->lose &= ~op1->match;
lose1 = op1->lose;
}
/* Because the bits that are variable in one opcode are constant in
another, it is important to order the opcodes in the right order. */
for (i = 0; i < 32; ++i)
{
unsigned long int x = 1 << i;
int x0 = (match0 & x) != 0;
int x1 = (match1 & x) != 0;
if (x0 != x1)
return x1 - x0;
}
for (i = 0; i < 32; ++i)
{
unsigned long int x = 1 << i;
int x0 = (lose0 & x) != 0;
int x1 = (lose1 & x) != 0;
if (x0 != x1)
return x1 - x0;
}
/* They are functionally equal. So as long as the opcode table is
valid, we can put whichever one first we want, on aesthetic grounds. */
/* Our first aesthetic ground is that aliases defer to real insns. */
{
int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
if (alias_diff != 0)
/* Put the one that isn't an alias first. */
return alias_diff;
}
/* Except for aliases, two "identical" instructions had
better have the same opcode. This is a sanity check on the table. */
i = strcmp (op0->name, op1->name);
if (i)
{
if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
return i;
else
fprintf (stderr,
/* xgettext:c-format */
_("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
op0->name, op1->name);
}
/* Fewer arguments are preferred. */
{
int length_diff = strlen (op0->args) - strlen (op1->args);
if (length_diff != 0)
/* Put the one with fewer arguments first. */
return length_diff;
}
/* Put 1+i before i+1. */
{
char *p0 = (char *) strchr (op0->args, '+');
char *p1 = (char *) strchr (op1->args, '+');
if (p0 && p1)
{
/* There is a plus in both operands. Note that a plus
sign cannot be the first character in args,
so the following [-1]'s are valid. */
if (p0[-1] == 'i' && p1[1] == 'i')
/* op0 is i+1 and op1 is 1+i, so op1 goes first. */
return 1;
if (p0[1] == 'i' && p1[-1] == 'i')
/* op0 is 1+i and op1 is i+1, so op0 goes first. */
return -1;
}
}
/* Put 1,i before i,1. */
{
int i0 = strncmp (op0->args, "i,1", 3) == 0;
int i1 = strncmp (op1->args, "i,1", 3) == 0;
if (i0 ^ i1)
return i0 - i1;
}
/* They are, as far as we can tell, identical.
Since qsort may have rearranged the table partially, there is
no way to tell which one was first in the opcode table as
written, so just say there are equal. */
/* ??? This is no longer true now that we sort a vector of pointers,
not the table itself. */
return 0;
}
/* Build a hash table from the opcode table.
OPCODE_TABLE is a sorted list of pointers into the opcode table. */
static void
build_hash_table (const sparc_opcode **opcode_table,
sparc_opcode_hash **hash_table,
int num_opcodes)
{
int i;
int hash_count[HASH_SIZE];
static sparc_opcode_hash *hash_buf = NULL;
/* Start at the end of the table and work backwards so that each
chain is sorted. */
memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
if (hash_buf != NULL)
free (hash_buf);
hash_buf = malloc (sizeof (* hash_buf) * num_opcodes);
for (i = num_opcodes - 1; i >= 0; --i)
{
int hash = HASH_INSN (opcode_table[i]->match);
sparc_opcode_hash *h = &hash_buf[i];
h->next = hash_table[hash];
h->opcode = opcode_table[i];
hash_table[hash] = h;
++hash_count[hash];
}
#if 0 /* for debugging */
{
int min_count = num_opcodes, max_count = 0;
int total;
for (i = 0; i < HASH_SIZE; ++i)
{
if (hash_count[i] < min_count)
min_count = hash_count[i];
if (hash_count[i] > max_count)
max_count = hash_count[i];
total += hash_count[i];
}
printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
min_count, max_count, (double) total / HASH_SIZE);
}
#endif
}
/* Print one instruction from MEMADDR on INFO->STREAM.
We suffix the instruction with a comment that gives the absolute
......@@ -2433,19 +2686,17 @@ static unsigned int current_arch_mask;
on that register. */
int
print_insn_sparc (memaddr, info)
bfd_vma memaddr;
disassemble_info *info;
print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
{
FILE *stream = info->stream;
bfd_byte buffer[4];
unsigned long insn;
register struct opcode_hash *op;
sparc_opcode_hash *op;
/* Nonzero of opcode table has been initialized. */
static int opcodes_initialized = 0;
/* bfd mach number of last call. */
static unsigned long current_mach = 0;
bfd_vma (*getword) PARAMS ((const unsigned char *));
bfd_vma (*getword) (const unsigned char *);
if (!opcodes_initialized
|| info->mach != current_mach)
......@@ -2455,8 +2706,8 @@ print_insn_sparc (memaddr, info)
current_arch_mask = compute_arch_mask (info->mach);
if (!opcodes_initialized)
sorted_opcodes = (const struct sparc_opcode **)
malloc (sparc_num_opcodes * sizeof (struct sparc_opcode *));
sorted_opcodes =
malloc (sparc_num_opcodes * sizeof (sparc_opcode *));
/* Reset the sorted table so we can resort it. */
for (i = 0; i < sparc_num_opcodes; ++i)
sorted_opcodes[i] = &sparc_opcodes[i];
......@@ -2471,6 +2722,7 @@ print_insn_sparc (memaddr, info)
{
int status =
(*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
......@@ -2487,14 +2739,14 @@ print_insn_sparc (memaddr, info)
insn = getword (buffer);
info->insn_info_valid = 1; /* We do return this info */
info->insn_type = dis_nonbranch; /* Assume non branch insn */
info->branch_delay_insns = 0; /* Assume no delay */
info->target = 0; /* Assume no target known */
info->insn_info_valid = 1; /* We do return this info. */
info->insn_type = dis_nonbranch; /* Assume non branch insn. */
info->branch_delay_insns = 0; /* Assume no delay. */
info->target = 0; /* Assume no target known. */
for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
{
const struct sparc_opcode *opcode = op->opcode;
const sparc_opcode *opcode = op->opcode;
/* If the insn isn't supported by the current architecture, skip it. */
if (! (opcode->architecture & current_arch_mask))
......@@ -2534,17 +2786,19 @@ print_insn_sparc (memaddr, info)
(*info->fprintf_func) (stream, opcode->name);
{
register const char *s;
const char *s;
if (opcode->args[0] != ',')
(*info->fprintf_func) (stream, " ");
for (s = opcode->args; *s != '\0'; ++s)
{
while (*s == ',')
{
(*info->fprintf_func) (stream, ",");
++s;
switch (*s) {
switch (*s)
{
case 'a':
(*info->fprintf_func) (stream, "a");
is_annulled = 1;
......@@ -2562,8 +2816,8 @@ print_insn_sparc (memaddr, info)
default:
break;
} /* switch on arg */
} /* while there are comma started args */
}
}
(*info->fprintf_func) (stream, " ");
......@@ -2571,8 +2825,8 @@ print_insn_sparc (memaddr, info)
{
case '+':
found_plus = 1;
/* Fall through. */
/* note fall-through */
default:
(*info->fprintf_func) (stream, "%c", *s);
break;
......@@ -2602,24 +2856,24 @@ print_insn_sparc (memaddr, info)
case 'e':
freg (X_RS1 (insn));
break;
case 'v': /* double/even */
case 'V': /* quad/multiple of 4 */
case 'v': /* Double/even. */
case 'V': /* Quad/multiple of 4. */
fregx (X_RS1 (insn));
break;
case 'f':
freg (X_RS2 (insn));
break;
case 'B': /* double/even */
case 'R': /* quad/multiple of 4 */
case 'B': /* Double/even. */
case 'R': /* Quad/multiple of 4. */
fregx (X_RS2 (insn));
break;
case 'g':
freg (X_RD (insn));
break;
case 'H': /* double/even */
case 'J': /* quad/multiple of 4 */
case 'H': /* Double/even. */
case 'J': /* Quad/multiple of 4. */
fregx (X_RD (insn));
break;
#undef freg
......@@ -2645,9 +2899,9 @@ print_insn_sparc (memaddr, info)
& ((int) X_IMM22 (insn) << 10)));
break;
case 'i': /* 13 bit immediate */
case 'I': /* 11 bit immediate */
case 'j': /* 10 bit immediate */
case 'i': /* 13 bit immediate. */
case 'I': /* 11 bit immediate. */
case 'j': /* 10 bit immediate. */
{
int imm;
......@@ -2675,8 +2929,8 @@ print_insn_sparc (memaddr, info)
}
break;
case 'X': /* 5 bit unsigned immediate */
case 'Y': /* 6 bit unsigned immediate */
case 'X': /* 5 bit unsigned immediate. */
case 'Y': /* 6 bit unsigned immediate. */
{
int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
......@@ -2688,7 +2942,7 @@ print_insn_sparc (memaddr, info)
break;
case '3':
(info->fprintf_func) (stream, "%d", X_IMM (insn, 3));
(info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
break;
case 'K':
......@@ -2763,7 +3017,7 @@ print_insn_sparc (memaddr, info)
case '?':
if (X_RS1 (insn) == 31)
(*info->fprintf_func) (stream, "%%ver");
else if ((unsigned) X_RS1 (insn) < 16)
else if ((unsigned) X_RS1 (insn) < 17)
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RS1 (insn)]);
else
......@@ -2771,13 +3025,29 @@ print_insn_sparc (memaddr, info)
break;
case '!':
if ((unsigned) X_RD (insn) < 15)
if ((unsigned) X_RD (insn) < 17)
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RD (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
case '$':
if ((unsigned) X_RS1 (insn) < 32)
(*info->fprintf_func) (stream, "%%%s",
v9_hpriv_reg_names[X_RS1 (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
case '%':
if ((unsigned) X_RD (insn) < 32)
(*info->fprintf_func) (stream, "%%%s",
v9_hpriv_reg_names[X_RD (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
case '/':
if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
(*info->fprintf_func) (stream, "%%reserved");
......@@ -2801,16 +3071,16 @@ print_insn_sparc (memaddr, info)
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
(*info->fprintf_func) (stream, "%d", X_RD (insn));
(*info->fprintf_func) (stream, "%ld", X_RD (insn));
break;
}
case 'M':
(*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
(*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
break;
case 'm':
(*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
(*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
break;
case 'L':
......@@ -2842,7 +3112,7 @@ print_insn_sparc (memaddr, info)
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
(*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
(*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
break;
}
......@@ -2875,7 +3145,7 @@ print_insn_sparc (memaddr, info)
break;
case 'x':
(*info->fprintf_func) (stream, "%d",
(*info->fprintf_func) (stream, "%ld",
((X_LDST_I (insn) << 8)
+ X_ASI (insn)));
break;
......@@ -2911,26 +3181,33 @@ print_insn_sparc (memaddr, info)
unsigned long prev_insn;
int errcode;
if (memaddr >= 4)
errcode =
(*info->read_memory_func)
(memaddr - 4, buffer, sizeof (buffer), info);
else
errcode = 1;
prev_insn = getword (buffer);
if (errcode == 0)
{
/* If it is a delayed branch, we need to look at the
instruction before the delayed branch. This handles
sequences such as
sequences such as:
sethi %o1, %hi(_foo), %o1
call _printf
or %o1, %lo(_foo), %o1
*/
or %o1, %lo(_foo), %o1 */
if (is_delayed_branch (prev_insn))
{
if (memaddr >= 8)
errcode = (*info->read_memory_func)
(memaddr - 8, buffer, sizeof (buffer), info);
else
errcode = 1;
prev_insn = getword (buffer);
}
}
......@@ -2960,7 +3237,7 @@ print_insn_sparc (memaddr, info)
if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
{
/* FIXME -- check is_annulled flag */
/* FIXME -- check is_annulled flag. */
if (opcode->flags & F_UNBR)
info->insn_type = dis_branch;
if (opcode->flags & F_CONDBR)
......@@ -2975,236 +3252,7 @@ print_insn_sparc (memaddr, info)
}
}
info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
(*info->fprintf_func) (stream, _("unknown"));
return sizeof (buffer);
}
/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
static int
compute_arch_mask (mach)
unsigned long mach;
{
switch (mach)
{
case 0 :
case bfd_mach_sparc :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
case bfd_mach_sparc_sparclet :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
case bfd_mach_sparc_sparclite :
case bfd_mach_sparc_sparclite_le :
/* sparclites insns are recognized by default (because that's how
they've always been treated, for better or worse). Kludge this by
indicating generic v8 is also selected. */
return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
| SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
case bfd_mach_sparc_v8plus :
case bfd_mach_sparc_v9 :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
case bfd_mach_sparc_v8plusa :
case bfd_mach_sparc_v9a :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
case bfd_mach_sparc_v8plusb :
case bfd_mach_sparc_v9b :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
}
abort ();
}
/* Compare opcodes A and B. */
static int
compare_opcodes (const void *a, const void *b)
{
struct sparc_opcode *op0 = * (struct sparc_opcode **) a;
struct sparc_opcode *op1 = * (struct sparc_opcode **) b;
unsigned long int match0 = op0->match, match1 = op1->match;
unsigned long int lose0 = op0->lose, lose1 = op1->lose;
register unsigned int i;
/* If one (and only one) insn isn't supported by the current architecture,
prefer the one that is. If neither are supported, but they're both for
the same architecture, continue processing. Otherwise (both unsupported
and for different architectures), prefer lower numbered arch's (fudged
by comparing the bitmasks). */
if (op0->architecture & current_arch_mask)
{
if (! (op1->architecture & current_arch_mask))
return -1;
}
else
{
if (op1->architecture & current_arch_mask)
return 1;
else if (op0->architecture != op1->architecture)
return op0->architecture - op1->architecture;
}
/* If a bit is set in both match and lose, there is something
wrong with the opcode table. */
if (match0 & lose0)
{
fprintf
(stderr,
/* xgettext:c-format */
_("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
op0->name, match0, lose0);
op0->lose &= ~op0->match;
lose0 = op0->lose;
}
if (match1 & lose1)
{
fprintf
(stderr,
/* xgettext:c-format */
_("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
op1->name, match1, lose1);
op1->lose &= ~op1->match;
lose1 = op1->lose;
}
/* Because the bits that are variable in one opcode are constant in
another, it is important to order the opcodes in the right order. */
for (i = 0; i < 32; ++i)
{
unsigned long int x = 1 << i;
int x0 = (match0 & x) != 0;
int x1 = (match1 & x) != 0;
if (x0 != x1)
return x1 - x0;
}
for (i = 0; i < 32; ++i)
{
unsigned long int x = 1 << i;
int x0 = (lose0 & x) != 0;
int x1 = (lose1 & x) != 0;
if (x0 != x1)
return x1 - x0;
}
/* They are functionally equal. So as long as the opcode table is
valid, we can put whichever one first we want, on aesthetic grounds. */
/* Our first aesthetic ground is that aliases defer to real insns. */
{
int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
if (alias_diff != 0)
/* Put the one that isn't an alias first. */
return alias_diff;
}
/* Except for aliases, two "identical" instructions had
better have the same opcode. This is a sanity check on the table. */
i = strcmp (op0->name, op1->name);
if (i)
{
if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
return i;
else
fprintf (stderr,
/* xgettext:c-format */
_("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
op0->name, op1->name);
}
/* Fewer arguments are preferred. */
{
int length_diff = strlen (op0->args) - strlen (op1->args);
if (length_diff != 0)
/* Put the one with fewer arguments first. */
return length_diff;
}
/* Put 1+i before i+1. */
{
char *p0 = (char *) strchr (op0->args, '+');
char *p1 = (char *) strchr (op1->args, '+');
if (p0 && p1)
{
/* There is a plus in both operands. Note that a plus
sign cannot be the first character in args,
so the following [-1]'s are valid. */
if (p0[-1] == 'i' && p1[1] == 'i')
/* op0 is i+1 and op1 is 1+i, so op1 goes first. */
return 1;
if (p0[1] == 'i' && p1[-1] == 'i')
/* op0 is 1+i and op1 is i+1, so op0 goes first. */
return -1;
}
}
/* Put 1,i before i,1. */
{
int i0 = strncmp (op0->args, "i,1", 3) == 0;
int i1 = strncmp (op1->args, "i,1", 3) == 0;
if (i0 ^ i1)
return i0 - i1;
}
/* They are, as far as we can tell, identical.
Since qsort may have rearranged the table partially, there is
no way to tell which one was first in the opcode table as
written, so just say there are equal. */
/* ??? This is no longer true now that we sort a vector of pointers,
not the table itself. */
return 0;
}
/* Build a hash table from the opcode table.
OPCODE_TABLE is a sorted list of pointers into the opcode table. */
static void
build_hash_table (opcode_table, hash_table, num_opcodes)
const struct sparc_opcode **opcode_table;
struct opcode_hash **hash_table;
int num_opcodes;
{
register int i;
int hash_count[HASH_SIZE];
static struct opcode_hash *hash_buf = NULL;
/* Start at the end of the table and work backwards so that each
chain is sorted. */
memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
if (hash_buf != NULL)
free (hash_buf);
hash_buf = (struct opcode_hash *) malloc (sizeof (struct opcode_hash) * num_opcodes);
for (i = num_opcodes - 1; i >= 0; --i)
{
register int hash = HASH_INSN (opcode_table[i]->match);
register struct opcode_hash *h = &hash_buf[i];
h->next = hash_table[hash];
h->opcode = opcode_table[i];
hash_table[hash] = h;
++hash_count[hash];
}
#if 0 /* for debugging */
{
int min_count = num_opcodes, max_count = 0;
int total;
for (i = 0; i < HASH_SIZE; ++i)
{
if (hash_count[i] < min_count)
min_count = hash_count[i];
if (hash_count[i] > max_count)
max_count = hash_count[i];
total += hash_count[i];
}
printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
min_count, max_count, (double) total / HASH_SIZE);
}
#endif
}
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或