arm_gic: handle banked enable bits for per-cpu interrupts
The first enable set/clear register (which controls the PPIs and SGIs) is supposed to be banked for each processor. Currently it is just handled globally and this prevents recent SMP Linux kernels from booting, because CPU0 stops receiving localtimer interrupts when CPU1 disables them locally. To fix this, allow the enable bits to be enabled per-cpu. For SPIs, always enable/disable ALL_CPU_MASK. Signed-off-by: NRabin Vincent <rabin@rab.in> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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