From 35ac9e342e008e3d47ef18d33a6977fdb99de9cd Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Mon, 5 Oct 2015 14:45:45 +0100 Subject: [PATCH] target-mips: Set Config5.XNP for R6 cores Set Config5.XNP for R6 cores to indicate the extended LL/SC family of instructions NOT present. Signed-off-by: Yongbok Kim Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- target-mips/translate_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 1b45884e9b..bb33c7cfeb 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -447,7 +447,7 @@ static const mips_def_t mips_defs[] = (1 << CP0C3_RXI) | (1U << CP0C3_M), .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | (3 << CP0C4_IE) | (1U << CP0C4_M), - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), .CP0_LLAddr_rw_bitmask = 0, @@ -665,7 +665,7 @@ static const mips_def_t mips_defs[] = (1 << CP0C3_RXI) | (1 << CP0C3_LPA), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | (0xfc << CP0C4_KScrExist), - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB), + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), .CP0_LLAddr_rw_bitmask = 0, -- GitLab