From 2c9adbda721c9996ec6b371cac4a00c1164b818e Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 7 Dec 2010 15:37:34 +0000 Subject: [PATCH] ARM: fix ldrexd/strexd Correct ldrexd and strexd code to always read and write the high word of the 64-bit value from addr+4. Also make ldrexd and strexd agree that for a 64 bit value the address in env->exclusive_addr is that of the low word. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/670883 Signed-off-by: Peter Maydell Reviewed-by: Nathan Froyd --- linux-user/main.c | 2 +- target-arm/translate.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 7d41d4ab88..0d627d68dd 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -589,7 +589,7 @@ static int do_strex(CPUARMState *env) } if (size == 3) { val = env->regs[(env->exclusive_info >> 12) & 0xf]; - segv = put_user_u32(val, addr); + segv = put_user_u32(val, addr + 4); if (segv) { env->cp15.c6_data = addr + 4; goto done; diff --git a/target-arm/translate.c b/target-arm/translate.c index bf1e643b53..7ee5375373 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5926,8 +5926,10 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, tcg_gen_mov_i32(cpu_exclusive_val, tmp); store_reg(s, rt, tmp); if (size == 3) { - tcg_gen_addi_i32(addr, addr, 4); - tmp = gen_ld32(addr, IS_USER(s)); + TCGv tmp2 = new_tmp(); + tcg_gen_addi_i32(tmp2, addr, 4); + tmp = gen_ld32(tmp2, IS_USER(s)); + dead_tmp(tmp2); tcg_gen_mov_i32(cpu_exclusive_high, tmp); store_reg(s, rt2, tmp); } @@ -5987,7 +5989,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, if (size == 3) { TCGv tmp2 = new_tmp(); tcg_gen_addi_i32(tmp2, addr, 4); - tmp = gen_ld32(addr, IS_USER(s)); + tmp = gen_ld32(tmp2, IS_USER(s)); dead_tmp(tmp2); tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label); dead_tmp(tmp); -- GitLab