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提交 2a24a7ba 编写于 作者: Y Yongbok Kim 提交者： Leon Alrae
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target-mips: microMIPS32 R6 POOL32F instructions 

Add new microMIPS32 Release 6 POOL32F instructions
Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: NLeon Alrae <leon.alrae@imgtec.com>
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NLeon Alrae <leon.alrae@imgtec.com>
上级 e0332095
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内联 并排
Showing with 199 addition and 32 deletion
target-mips/translate.c
浏览文件 @ 2a24a7ba
......@@ -14209,6 +14209,14 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
goto pool32f_invalid;
}
break;
case CMP_CONDN_S:
check_insn(ctx, ISA_MIPS32R6);
gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
break;
case CMP_CONDN_D:
check_insn(ctx, ISA_MIPS32R6);
gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd);
break;
case POOL32FXF:
gen_pool32fxf(ctx, rt, rs);
break;
......@@ -14237,6 +14245,19 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
goto pool32f_invalid;
}
break;
case MIN_FMT:
check_insn(ctx, ISA_MIPS32R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
break;
default:
goto pool32f_invalid;
}
break;
case 0x08:
/* [LS][WDU]XC1 */
switch ((ctx->opcode >> 6) & 0x7) {
......@@ -14270,6 +14291,19 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
goto pool32f_invalid;
}
break;
case MAX_FMT:
check_insn(ctx, ISA_MIPS32R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
break;
default:
goto pool32f_invalid;
}
break;
case 0x18:
/* 3D insns */
check_insn_opc_removed(ctx, ISA_MIPS32R6);
......@@ -14318,11 +14352,25 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case 0x20:
/* MOV[FT].fmt and PREFX */
/* MOV[FT].fmt, PREFX, RINT.fmt, CLASS.fmt*/
cc = (ctx->opcode >> 13) & 0x7;
fmt = (ctx->opcode >> 9) & 0x3;
switch ((ctx->opcode >> 6) & 0x7) {
case MOVF_FMT:
case MOVF_FMT: /* RINT_FMT */
if (ctx->insn_flags & ISA_MIPS32R6) {
/* RINT_FMT */
switch (fmt) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
break;
default:
goto pool32f_invalid;
}
} else {
/* MOVF_FMT */
switch (fmt) {
case FMT_SDPS_S:
gen_movcf_s(ctx, rs, rt, cc, 0);
......@@ -14337,8 +14385,23 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
default:
goto pool32f_invalid;
}
}
break;
case MOVT_FMT:
case MOVT_FMT: /* CLASS_FMT */
if (ctx->insn_flags & ISA_MIPS32R6) {
/* CLASS_FMT */
switch (fmt) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
break;
default:
goto pool32f_invalid;
}
} else {
/* MOVT_FMT */
switch (fmt) {
case FMT_SDPS_S:
gen_movcf_s(ctx, rs, rt, cc, 1);
......@@ -14353,6 +14416,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
default:
goto pool32f_invalid;
}
}
break;
case PREFX:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
......@@ -14376,6 +14440,32 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
default: \
goto pool32f_invalid; \
}
case MINA_FMT:
check_insn(ctx, ISA_MIPS32R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
break;
default:
goto pool32f_invalid;
}
break;
case MAXA_FMT:
check_insn(ctx, ISA_MIPS32R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
break;
case FMT_SDPS_D:
gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
break;
default:
goto pool32f_invalid;
}
break;
case 0x30:
/* regular FP ops */
switch ((ctx->opcode >> 6) & 0x3) {
......@@ -14404,13 +14494,90 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case 0x38:
/* cmovs */
switch ((ctx->opcode >> 6) & 0x3) {
case MOVN_FMT:
switch ((ctx->opcode >> 6) & 0x7) {
case MOVN_FMT: /* SELNEZ_FMT */
if (ctx->insn_flags & ISA_MIPS32R6) {
/* SELNEZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
break;
case FMT_SDPS_D:
gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
}
} else {
/* MOVN_FMT */
FINSN_3ARG_SDPS(MOVN);
}
break;
case MOVN_FMT_04:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
FINSN_3ARG_SDPS(MOVN);
break;
case MOVZ_FMT: /* SELEQZ_FMT */
if (ctx->insn_flags & ISA_MIPS32R6) {
/* SELEQZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
break;
case FMT_SDPS_D:
gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
}
} else {
/* MOVZ_FMT */
FINSN_3ARG_SDPS(MOVZ);
}
break;
case MOVZ_FMT:
case MOVZ_FMT_05:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
FINSN_3ARG_SDPS(MOVZ);
break;
case SEL_FMT:
check_insn(ctx, ISA_MIPS32R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
break;
case FMT_SDPS_D:
gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
}
break;
case MADDF_FMT:
check_insn(ctx, ISA_MIPS32R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
mips32_op = OPC_MADDF_S;
goto do_fpop;
case FMT_SDPS_D:
mips32_op = OPC_MADDF_D;
goto do_fpop;
default:
goto pool32f_invalid;
}
break;
case MSUBF_FMT:
check_insn(ctx, ISA_MIPS32R6);
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
mips32_op = OPC_MSUBF_S;
goto do_fpop;
case FMT_SDPS_D:
mips32_op = OPC_MSUBF_D;
goto do_fpop;
default:
goto pool32f_invalid;
}
break;
default:
goto pool32f_invalid;
}
......
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