From 263273bc988e677ebadeaf7d0e49f6792a112db5 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 14 Feb 2020 11:46:41 -0800 Subject: [PATCH] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX Writes to AdvSIMD registers flush the bits above 128. Signed-off-by: Richard Henderson Message-id: 20200214194643.23317-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 620a429067..096a854aed 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6964,6 +6964,7 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_resl); write_vec_element(s, tcg_resh, rd, 1, MO_64); tcg_temp_free_i64(tcg_resh); + clear_vec_high(s, true, rd); } /* ZIP/UZP/TRN -- GitLab