Remove synonymous in PowerPC MSR bits definitions.

Fix MSR EP bit buggy definition.
Remove unuseful MSR flags.
Fix MSR bits and flags definitions for most supported PowerPC implementations.
Add MSR definitions/flags constistency checks and optional dump.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3354 c046a42c-6fe2-441c-8c8c-71466251a162

target-ppc/cpu.h

@@ -354,8 +354,7 @@ union ppc_tlb_t {
 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 #define MSR_KEY  19 /* key bit on 603e                                       */
-#define MSR_POW  18 /* Power management                             x        */
-#define MSR_WE   18 /* Wait state enable on embedded PowerPC        x        */
+#define MSR_POW  18 /* Power management                                      */
 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
@@ -371,11 +370,10 @@ union ppc_tlb_t {
 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 #define MSR_AL   7  /* AL bit on POWER                                       */
-#define MSR_IP   6  /* Interrupt prefix                                      */
+#define MSR_EP   3  /* Exception prefix on 601                               */
 #define MSR_IR   5  /* Instruction relocate                                  */
 #define MSR_DR   4  /* Data relocate                                         */
-#define MSR_PE   3  /* Protection enable on 403                     x        */
-#define MSR_EP   3  /* Exception prefix on 601                      x        */
+#define MSR_PE   3  /* Protection enable on 403                              */
 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 #define MSR_RI   1  /* Recoverable interrupt                        1        */
@@ -392,7 +390,6 @@ union ppc_tlb_t {
 #define msr_sa   env->msr[MSR_SA]
 #define msr_key  env->msr[MSR_KEY]
 #define msr_pow  env->msr[MSR_POW]
-#define msr_we   env->msr[MSR_WE]
 #define msr_tgpr env->msr[MSR_TGPR]
 #define msr_ce   env->msr[MSR_CE]
 #define msr_ile  env->msr[MSR_ILE]
@@ -408,7 +405,6 @@ union ppc_tlb_t {
 #define msr_de   env->msr[MSR_DE]
 #define msr_fe1  env->msr[MSR_FE1]
 #define msr_al   env->msr[MSR_AL]
-#define msr_ip   env->msr[MSR_IP]
 #define msr_ir   env->msr[MSR_IR]
 #define msr_dr   env->msr[MSR_DR]
 #define msr_pe   env->msr[MSR_PE]
@@ -419,30 +415,23 @@ union ppc_tlb_t {
 #define msr_le   env->msr[MSR_LE]
 
 enum {
-    /* Beware that MSR bits are given using IBM standard (ie MSB is 0 !)     */
     POWERPC_FLAG_NONE = 0x00000000,
     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
     POWERPC_FLAG_SPE  = 0x00000001,
     POWERPC_FLAG_VRE  = 0x00000002,
-    /* Flag for MSR bit 18 may not be needed...                              */
-    POWERPC_FLAG_POW  = 0x00000004,
-    POWERPC_FLAG_WE   = 0x00000008,
     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
-    POWERPC_FLAG_TGPR = 0x00000010,
-    POWERPC_FLAG_CE   = 0x00000020,
+    POWERPC_FLAG_TGPR = 0x00000004,
+    POWERPC_FLAG_CE   = 0x00000008,
     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
-    POWERPC_FLAG_SE   = 0x00000040,
-    POWERPC_FLAG_DWE  = 0x00000080,
-    POWERPC_FLAG_UBLE = 0x00000100,
+    POWERPC_FLAG_SE   = 0x00000010,
+    POWERPC_FLAG_DWE  = 0x00000020,
+    POWERPC_FLAG_UBLE = 0x00000040,
     /* Flag for MSR bit 9 signification (BE/DE)                              */
-    POWERPC_FLAG_BE   = 0x00000200,
-    POWERPC_FLAG_DE   = 0x00000400,
-    /* Flag for MSR bit 3 signification (PE/EP)                              */
-    POWERPC_FLAG_PE   = 0x00000800,
-    POWERPC_FLAG_EP   = 0x00001000,
+    POWERPC_FLAG_BE   = 0x00000080,
+    POWERPC_FLAG_DE   = 0x00000100,
     /* Flag for MSR but 2 signification (PX/PMM)                             */
-    POWERPC_FLAG_PX   = 0x00002000,
-    POWERPC_FLAG_PMM  = 0x00004000,
+    POWERPC_FLAG_PX   = 0x00000200,
+    POWERPC_FLAG_PMM  = 0x00000400,
 };
 
 /*****************************************************************************/

target-ppc/helper.c

@@ -1964,7 +1964,7 @@ target_ulong do_load_msr (CPUPPCState *env)
         ((target_ulong)msr_ap   << MSR_AP)   |
         ((target_ulong)msr_sa   << MSR_SA)   |
         ((target_ulong)msr_key  << MSR_KEY)  |
-        ((target_ulong)msr_pow  << MSR_POW)  | /* POW / WE */
+        ((target_ulong)msr_pow  << MSR_POW)  |
         ((target_ulong)msr_tgpr << MSR_TGPR) | /* TGPR / CE */
         ((target_ulong)msr_ile  << MSR_ILE)  |
         ((target_ulong)msr_ee   << MSR_EE)   |
@@ -1976,10 +1976,10 @@ target_ulong do_load_msr (CPUPPCState *env)
         ((target_ulong)msr_be   << MSR_BE)   | /* BE / DE */
         ((target_ulong)msr_fe1  << MSR_FE1)  |
         ((target_ulong)msr_al   << MSR_AL)   |
-        ((target_ulong)msr_ip   << MSR_IP)   |
-        ((target_ulong)msr_ir   << MSR_IR)   | /* IR / IS */
-        ((target_ulong)msr_dr   << MSR_DR)   | /* DR / DS */
-        ((target_ulong)msr_pe   << MSR_PE)   | /* PE / EP */
+        ((target_ulong)msr_ep   << MSR_EP)   |
+        ((target_ulong)msr_ir   << MSR_IR)   |
+        ((target_ulong)msr_dr   << MSR_DR)   |
+        ((target_ulong)msr_pe   << MSR_PE)   |
         ((target_ulong)msr_px   << MSR_PX)   | /* PX / PMM */
         ((target_ulong)msr_ri   << MSR_RI)   |
         ((target_ulong)msr_le   << MSR_LE);
@@ -2017,7 +2017,7 @@ int do_store_msr (CPUPPCState *env, target_ulong value)
     msr_ap   = (value >> MSR_AP)   & 1;
     msr_sa   = (value >> MSR_SA)   & 1;
     msr_key  = (value >> MSR_KEY)  & 1;
-    msr_pow  = (value >> MSR_POW)  & 1; /* POW / WE */
+    msr_pow  = (value >> MSR_POW)  & 1;
     msr_tgpr = (value >> MSR_TGPR) & 1; /* TGPR / CE */
     msr_ile  = (value >> MSR_ILE)  & 1;
     msr_ee   = (value >> MSR_EE)   & 1;
@@ -2029,10 +2029,10 @@ int do_store_msr (CPUPPCState *env, target_ulong value)
     msr_be   = (value >> MSR_BE)   & 1; /* BE / DE */
     msr_fe1  = (value >> MSR_FE1)  & 1;
     msr_al   = (value >> MSR_AL)   & 1;
-    msr_ip   = (value >> MSR_IP)   & 1;
-    msr_ir   = (value >> MSR_IR)   & 1; /* IR / IS */
-    msr_dr   = (value >> MSR_DR)   & 1; /* DR / DS */
-    msr_pe   = (value >> MSR_PE)   & 1; /* PE / EP */
+    msr_ep   = (value >> MSR_EP)   & 1;
+    msr_ir   = (value >> MSR_IR)   & 1;
+    msr_dr   = (value >> MSR_DR)   & 1;
+    msr_pe   = (value >> MSR_PE)   & 1;
     msr_px   = (value >> MSR_PX)   & 1; /* PX / PMM */
     msr_ri   = (value >> MSR_RI)   & 1;
     msr_le   = (value >> MSR_LE)   & 1;