hw/intc/arm_gic: add tracepoints
These are obviously critical to understanding interrupt delivery: gic_enable_irq gic_disable_irq gic_set_irq (inbound irq from device models) gic_update_set_irq (outbound irq to CPU) gic_acknowledge_irq The only one that I think might raise eyebrows is gic_update_bestirq, but I've (sadly) debugged problems that ended up being caused by unexpected priorities. Knowing that the GIC has an irq ready, but doesn't deliver to the CPU due to priority, has also proven important. Signed-off-by: NHollis Blanchard <hollis_blanchard@mentor.com> Message-id: 1461252281-22399-1-git-send-email-hollis_blanchard@mentor.com Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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