From 1bf5902de03732d4067c4e90171a1741d6542c45 Mon Sep 17 00:00:00 2001
From: Yongbok Kim <yongbok.kim@imgtec.com>
Date: Thu, 25 Jun 2015 00:24:13 +0100
Subject: [PATCH] target-mips: fix {RD, WR}PGPR in microMIPS

rt, rs were swapped

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8547e2d04d..02c2523207 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -13001,12 +13001,12 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
         case RDPGPR:
             check_cp0_enabled(ctx);
             check_insn(ctx, ISA_MIPS32R2);
-            gen_load_srsgpr(rt, rs);
+            gen_load_srsgpr(rs, rt);
             break;
         case WRPGPR:
             check_cp0_enabled(ctx);
             check_insn(ctx, ISA_MIPS32R2);
-            gen_store_srsgpr(rt, rs);
+            gen_store_srsgpr(rs, rt);
             break;
         default:
             goto pool32axf_invalid;
-- 
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