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提交 19cbd87c 编写于 作者: E Eduardo Habkost
浏览文件
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target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_* 

They are helpers for the ZMMReg fields, so name them accordingly.

This is just a global search+replace, no other changes are being
introduced.
Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
上级 fa451874
隐藏空白更改
内联 并排
Showing with 300 addition and 300 deletion
target-i386/cpu.h
浏览文件 @ 19cbd87c
...@@ -753,24 +753,24 @@ typedef struct BNDCSReg { ...@@ -753,24 +753,24 @@ typedef struct BNDCSReg {
} BNDCSReg; } BNDCSReg;
#ifdef HOST_WORDS_BIGENDIAN #ifdef HOST_WORDS_BIGENDIAN
#define XMM_B(n) _b[63 - (n)] #define ZMM_B(n) _b[63 - (n)]
#define XMM_W(n) _w[31 - (n)] #define ZMM_W(n) _w[31 - (n)]
#define XMM_L(n) _l[15 - (n)] #define ZMM_L(n) _l[15 - (n)]
#define XMM_S(n) _s[15 - (n)] #define ZMM_S(n) _s[15 - (n)]
#define XMM_Q(n) _q[7 - (n)] #define ZMM_Q(n) _q[7 - (n)]
#define XMM_D(n) _d[7 - (n)] #define ZMM_D(n) _d[7 - (n)]
#define MMX_B(n) _b[7 - (n)] #define MMX_B(n) _b[7 - (n)]
#define MMX_W(n) _w[3 - (n)] #define MMX_W(n) _w[3 - (n)]
#define MMX_L(n) _l[1 - (n)] #define MMX_L(n) _l[1 - (n)]
#define MMX_S(n) _s[1 - (n)] #define MMX_S(n) _s[1 - (n)]
#else #else
#define XMM_B(n) _b[n] #define ZMM_B(n) _b[n]
#define XMM_W(n) _w[n] #define ZMM_W(n) _w[n]
#define XMM_L(n) _l[n] #define ZMM_L(n) _l[n]
#define XMM_S(n) _s[n] #define ZMM_S(n) _s[n]
#define XMM_Q(n) _q[n] #define ZMM_Q(n) _q[n]
#define XMM_D(n) _d[n] #define ZMM_D(n) _d[n]
#define MMX_B(n) _b[n] #define MMX_B(n) _b[n]
#define MMX_W(n) _w[n] #define MMX_W(n) _w[n]
......
target-i386/fpu_helper.c
浏览文件 @ 19cbd87c
...@@ -1169,8 +1169,8 @@ static void do_fxsave(CPUX86State *env, target_ulong ptr, int data64, ...@@ -1169,8 +1169,8 @@ static void do_fxsave(CPUX86State *env, target_ulong ptr, int data64,
|| (env->hflags & HF_CPL_MASK) || (env->hflags & HF_CPL_MASK)
|| !(env->hflags & HF_LMA_MASK)) { || !(env->hflags & HF_LMA_MASK)) {
for (i = 0; i < nb_xmm_regs; i++) { for (i = 0; i < nb_xmm_regs; i++) {
cpu_stq_data_ra(env, addr, env->xmm_regs[i].XMM_Q(0), retaddr); cpu_stq_data_ra(env, addr, env->xmm_regs[i].ZMM_Q(0), retaddr);
cpu_stq_data_ra(env, addr + 8, env->xmm_regs[i].XMM_Q(1), retaddr); cpu_stq_data_ra(env, addr + 8, env->xmm_regs[i].ZMM_Q(1), retaddr);
addr += 16; addr += 16;
} }
} }
...@@ -1226,8 +1226,8 @@ static void do_fxrstor(CPUX86State *env, target_ulong ptr, int data64, ...@@ -1226,8 +1226,8 @@ static void do_fxrstor(CPUX86State *env, target_ulong ptr, int data64,
|| (env->hflags & HF_CPL_MASK) || (env->hflags & HF_CPL_MASK)
|| !(env->hflags & HF_LMA_MASK)) { || !(env->hflags & HF_LMA_MASK)) {
for (i = 0; i < nb_xmm_regs; i++) { for (i = 0; i < nb_xmm_regs; i++) {
env->xmm_regs[i].XMM_Q(0) = cpu_ldq_data_ra(env, addr, retaddr); env->xmm_regs[i].ZMM_Q(0) = cpu_ldq_data_ra(env, addr, retaddr);
env->xmm_regs[i].XMM_Q(1) = cpu_ldq_data_ra(env, addr + 8, retaddr); env->xmm_regs[i].ZMM_Q(1) = cpu_ldq_data_ra(env, addr + 8, retaddr);
addr += 16; addr += 16;
} }
} }
......
target-i386/gdbstub.c
浏览文件 @ 19cbd87c
...@@ -61,8 +61,8 @@ int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) ...@@ -61,8 +61,8 @@ int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
n -= IDX_XMM_REGS; n -= IDX_XMM_REGS;
if (n < CPU_NB_REGS32 || if (n < CPU_NB_REGS32 ||
(TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) { (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0)); stq_p(mem_buf, env->xmm_regs[n].ZMM_Q(0));
stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1)); stq_p(mem_buf + 8, env->xmm_regs[n].ZMM_Q(1));
return 16; return 16;
} }
} else { } else {
...@@ -170,8 +170,8 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) ...@@ -170,8 +170,8 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
n -= IDX_XMM_REGS; n -= IDX_XMM_REGS;
if (n < CPU_NB_REGS32 || if (n < CPU_NB_REGS32 ||
(TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) { (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf); env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8); env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
return 16; return 16;
} }
} else { } else {
......
target-i386/helper.c
浏览文件 @ 19cbd87c
...@@ -535,10 +535,10 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, ...@@ -535,10 +535,10 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
for(i=0;i<nb;i++) { for(i=0;i<nb;i++) {
cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x", cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
i, i,
env->xmm_regs[i].XMM_L(3), env->xmm_regs[i].ZMM_L(3),
env->xmm_regs[i].XMM_L(2), env->xmm_regs[i].ZMM_L(2),
env->xmm_regs[i].XMM_L(1), env->xmm_regs[i].ZMM_L(1),
env->xmm_regs[i].XMM_L(0)); env->xmm_regs[i].ZMM_L(0));
if ((i & 1) == 1) if ((i & 1) == 1)
cpu_fprintf(f, "\n"); cpu_fprintf(f, "\n");
else else
......
target-i386/kvm.c
浏览文件 @ 19cbd87c
...@@ -1237,8 +1237,8 @@ static int kvm_put_fpu(X86CPU *cpu) ...@@ -1237,8 +1237,8 @@ static int kvm_put_fpu(X86CPU *cpu)
} }
memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
for (i = 0; i < CPU_NB_REGS; i++) { for (i = 0; i < CPU_NB_REGS; i++) {
stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0)); stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1)); stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
} }
fpu.mxcsr = env->mxcsr; fpu.mxcsr = env->mxcsr;
...@@ -1299,14 +1299,14 @@ static int kvm_put_xsave(X86CPU *cpu) ...@@ -1299,14 +1299,14 @@ static int kvm_put_xsave(X86CPU *cpu)
ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE]; ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256]; zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) { for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
stq_p(xmm, env->xmm_regs[i].XMM_Q(0)); stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1)); stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
stq_p(ymmh, env->xmm_regs[i].XMM_Q(2)); stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3)); stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
stq_p(zmmh, env->xmm_regs[i].XMM_Q(4)); stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5)); stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6)); stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7)); stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
} }
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
...@@ -1665,8 +1665,8 @@ static int kvm_get_fpu(X86CPU *cpu) ...@@ -1665,8 +1665,8 @@ static int kvm_get_fpu(X86CPU *cpu)
} }
memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
for (i = 0; i < CPU_NB_REGS; i++) { for (i = 0; i < CPU_NB_REGS; i++) {
env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]); env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]); env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
} }
env->mxcsr = fpu.mxcsr; env->mxcsr = fpu.mxcsr;
...@@ -1717,14 +1717,14 @@ static int kvm_get_xsave(X86CPU *cpu) ...@@ -1717,14 +1717,14 @@ static int kvm_get_xsave(X86CPU *cpu)
ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE]; ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256]; zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) { for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm); env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8); env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh); env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8); env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh); env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8); env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16); env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24); env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
} }
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
......
target-i386/machine.c
浏览文件 @ 19cbd87c
...@@ -36,8 +36,8 @@ static const VMStateDescription vmstate_xmm_reg = { ...@@ -36,8 +36,8 @@ static const VMStateDescription vmstate_xmm_reg = {
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT64(XMM_Q(0), ZMMReg), VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
VMSTATE_UINT64(XMM_Q(1), ZMMReg), VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
...@@ -52,8 +52,8 @@ static const VMStateDescription vmstate_ymmh_reg = { ...@@ -52,8 +52,8 @@ static const VMStateDescription vmstate_ymmh_reg = {
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT64(XMM_Q(2), ZMMReg), VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
VMSTATE_UINT64(XMM_Q(3), ZMMReg), VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
...@@ -67,10 +67,10 @@ static const VMStateDescription vmstate_zmmh_reg = { ...@@ -67,10 +67,10 @@ static const VMStateDescription vmstate_zmmh_reg = {
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT64(XMM_Q(4), ZMMReg), VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
VMSTATE_UINT64(XMM_Q(5), ZMMReg), VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
VMSTATE_UINT64(XMM_Q(6), ZMMReg), VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
VMSTATE_UINT64(XMM_Q(7), ZMMReg), VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
...@@ -85,14 +85,14 @@ static const VMStateDescription vmstate_hi16_zmm_reg = { ...@@ -85,14 +85,14 @@ static const VMStateDescription vmstate_hi16_zmm_reg = {
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT64(XMM_Q(0), ZMMReg), VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
VMSTATE_UINT64(XMM_Q(1), ZMMReg), VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
VMSTATE_UINT64(XMM_Q(2), ZMMReg), VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
VMSTATE_UINT64(XMM_Q(3), ZMMReg), VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
VMSTATE_UINT64(XMM_Q(4), ZMMReg), VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
VMSTATE_UINT64(XMM_Q(5), ZMMReg), VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
VMSTATE_UINT64(XMM_Q(6), ZMMReg), VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
VMSTATE_UINT64(XMM_Q(7), ZMMReg), VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
...@@ -787,7 +787,7 @@ static bool avx512_needed(void *opaque) ...@@ -787,7 +787,7 @@ static bool avx512_needed(void *opaque)
} }
for (i = 0; i < CPU_NB_REGS; i++) { for (i = 0; i < CPU_NB_REGS; i++) {
#define ENV_XMM(reg, field) (env->xmm_regs[reg].XMM_Q(field)) #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field))
if (ENV_XMM(i, 4) || ENV_XMM(i, 6) || if (ENV_XMM(i, 4) || ENV_XMM(i, 6) ||
ENV_XMM(i, 5) || ENV_XMM(i, 7)) { ENV_XMM(i, 5) || ENV_XMM(i, 7)) {
return true; return true;
......
target-i386/ops_sse.h
浏览文件 @ 19cbd87c
...@@ -31,10 +31,10 @@ ...@@ -31,10 +31,10 @@
#else #else
#define Reg ZMMReg #define Reg ZMMReg
#define XMM_ONLY(...) __VA_ARGS__ #define XMM_ONLY(...) __VA_ARGS__
#define B(n) XMM_B(n) #define B(n) ZMM_B(n)
#define W(n) XMM_W(n) #define W(n) ZMM_W(n)
#define L(n) XMM_L(n) #define L(n) ZMM_L(n)
#define Q(n) XMM_Q(n) #define Q(n) ZMM_Q(n)
#define SUFFIX _xmm #define SUFFIX _xmm
#endif #endif
...@@ -582,26 +582,26 @@ void glue(helper_pshufhw, SUFFIX)(Reg *d, Reg *s, int order) ...@@ -582,26 +582,26 @@ void glue(helper_pshufhw, SUFFIX)(Reg *d, Reg *s, int order)
#define SSE_HELPER_S(name, F) \ #define SSE_HELPER_S(name, F) \
void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \ void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \
{ \ { \
d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ d->ZMM_S(0) = F(32, d->ZMM_S(0), s->ZMM_S(0)); \
d->XMM_S(1) = F(32, d->XMM_S(1), s->XMM_S(1)); \ d->ZMM_S(1) = F(32, d->ZMM_S(1), s->ZMM_S(1)); \
d->XMM_S(2) = F(32, d->XMM_S(2), s->XMM_S(2)); \ d->ZMM_S(2) = F(32, d->ZMM_S(2), s->ZMM_S(2)); \
d->XMM_S(3) = F(32, d->XMM_S(3), s->XMM_S(3)); \ d->ZMM_S(3) = F(32, d->ZMM_S(3), s->ZMM_S(3)); \
} \ } \
\ \
void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \ void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \
{ \ { \
d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ d->ZMM_S(0) = F(32, d->ZMM_S(0), s->ZMM_S(0)); \
} \ } \
\ \
void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \ void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \
{ \ { \
d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ d->ZMM_D(0) = F(64, d->ZMM_D(0), s->ZMM_D(0)); \
d->XMM_D(1) = F(64, d->XMM_D(1), s->XMM_D(1)); \ d->ZMM_D(1) = F(64, d->ZMM_D(1), s->ZMM_D(1)); \
} \ } \
\ \
void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \ void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \
{ \ { \
d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ d->ZMM_D(0) = F(64, d->ZMM_D(0), s->ZMM_D(0)); \
} }
#define FPU_ADD(size, a, b) float ## size ## _add(a, b, &env->sse_status) #define FPU_ADD(size, a, b) float ## size ## _add(a, b, &env->sse_status)
...@@ -633,216 +633,216 @@ void helper_cvtps2pd(CPUX86State *env, Reg *d, Reg *s) ...@@ -633,216 +633,216 @@ void helper_cvtps2pd(CPUX86State *env, Reg *d, Reg *s)
{ {
float32 s0, s1; float32 s0, s1;
s0 = s->XMM_S(0); s0 = s->ZMM_S(0);
s1 = s->XMM_S(1); s1 = s->ZMM_S(1);
d->XMM_D(0) = float32_to_float64(s0, &env->sse_status); d->ZMM_D(0) = float32_to_float64(s0, &env->sse_status);
d->XMM_D(1) = float32_to_float64(s1, &env->sse_status); d->ZMM_D(1) = float32_to_float64(s1, &env->sse_status);
} }
void helper_cvtpd2ps(CPUX86State *env, Reg *d, Reg *s) void helper_cvtpd2ps(CPUX86State *env, Reg *d, Reg *s)
{ {
d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status); d->ZMM_S(0) = float64_to_float32(s->ZMM_D(0), &env->sse_status);
d->XMM_S(1) = float64_to_float32(s->XMM_D(1), &env->sse_status); d->ZMM_S(1) = float64_to_float32(s->ZMM_D(1), &env->sse_status);
d->Q(1) = 0; d->Q(1) = 0;
} }
void helper_cvtss2sd(CPUX86State *env, Reg *d, Reg *s) void helper_cvtss2sd(CPUX86State *env, Reg *d, Reg *s)
{ {
d->XMM_D(0) = float32_to_float64(s->XMM_S(0), &env->sse_status); d->ZMM_D(0) = float32_to_float64(s->ZMM_S(0), &env->sse_status);
} }
void helper_cvtsd2ss(CPUX86State *env, Reg *d, Reg *s) void helper_cvtsd2ss(CPUX86State *env, Reg *d, Reg *s)
{ {
d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status); d->ZMM_S(0) = float64_to_float32(s->ZMM_D(0), &env->sse_status);
} }
/* integer to float */ /* integer to float */
void helper_cvtdq2ps(CPUX86State *env, Reg *d, Reg *s) void helper_cvtdq2ps(CPUX86State *env, Reg *d, Reg *s)
{ {
d->XMM_S(0) = int32_to_float32(s->XMM_L(0), &env->sse_status); d->ZMM_S(0) = int32_to_float32(s->ZMM_L(0), &env->sse_status);
d->XMM_S(1) = int32_to_float32(s->XMM_L(1), &env->sse_status); d->ZMM_S(1) = int32_to_float32(s->ZMM_L(1), &env->sse_status);
d->XMM_S(2) = int32_to_float32(s->XMM_L(2), &env->sse_status); d->ZMM_S(2) = int32_to_float32(s->ZMM_L(2), &env->sse_status);
d->XMM_S(3) = int32_to_float32(s->XMM_L(3), &env->sse_status); d->ZMM_S(3) = int32_to_float32(s->ZMM_L(3), &env->sse_status);
} }
void helper_cvtdq2pd(CPUX86State *env, Reg *d, Reg *s) void helper_cvtdq2pd(CPUX86State *env, Reg *d, Reg *s)
{ {
int32_t l0, l1; int32_t l0, l1;
l0 = (int32_t)s->XMM_L(0); l0 = (int32_t)s->ZMM_L(0);
l1 = (int32_t)s->XMM_L(1); l1 = (int32_t)s->ZMM_L(1);
d->XMM_D(0) = int32_to_float64(l0, &env->sse_status); d->ZMM_D(0) = int32_to_float64(l0, &env->sse_status);
d->XMM_D(1) = int32_to_float64(l1, &env->sse_status); d->ZMM_D(1) = int32_to_float64(l1, &env->sse_status);
} }
void helper_cvtpi2ps(CPUX86State *env, ZMMReg *d, MMXReg *s) void helper_cvtpi2ps(CPUX86State *env, ZMMReg *d, MMXReg *s)
{ {
d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status); d->ZMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status);
d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status); d->ZMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status);
} }
void helper_cvtpi2pd(CPUX86State *env, ZMMReg *d, MMXReg *s) void helper_cvtpi2pd(CPUX86State *env, ZMMReg *d, MMXReg *s)
{ {
d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status); d->ZMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status);
d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status); d->ZMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status);
} }
void helper_cvtsi2ss(CPUX86State *env, ZMMReg *d, uint32_t val) void helper_cvtsi2ss(CPUX86State *env, ZMMReg *d, uint32_t val)
{ {
d->XMM_S(0) = int32_to_float32(val, &env->sse_status); d->ZMM_S(0) = int32_to_float32(val, &env->sse_status);
} }
void helper_cvtsi2sd(CPUX86State *env, ZMMReg *d, uint32_t val) void helper_cvtsi2sd(CPUX86State *env, ZMMReg *d, uint32_t val)
{ {
d->XMM_D(0) = int32_to_float64(val, &env->sse_status); d->ZMM_D(0) = int32_to_float64(val, &env->sse_status);
} }
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
void helper_cvtsq2ss(CPUX86State *env, ZMMReg *d, uint64_t val) void helper_cvtsq2ss(CPUX86State *env, ZMMReg *d, uint64_t val)
{ {
d->XMM_S(0) = int64_to_float32(val, &env->sse_status); d->ZMM_S(0) = int64_to_float32(val, &env->sse_status);
} }
void helper_cvtsq2sd(CPUX86State *env, ZMMReg *d, uint64_t val) void helper_cvtsq2sd(CPUX86State *env, ZMMReg *d, uint64_t val)
{ {
d->XMM_D(0) = int64_to_float64(val, &env->sse_status); d->ZMM_D(0) = int64_to_float64(val, &env->sse_status);
} }
#endif #endif
/* float to integer */ /* float to integer */
void helper_cvtps2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_cvtps2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); d->ZMM_L(0) = float32_to_int32(s->ZMM_S(0), &env->sse_status);
d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); d->ZMM_L(1) = float32_to_int32(s->ZMM_S(1), &env->sse_status);
d->XMM_L(2) = float32_to_int32(s->XMM_S(2), &env->sse_status); d->ZMM_L(2) = float32_to_int32(s->ZMM_S(2), &env->sse_status);
d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status); d->ZMM_L(3) = float32_to_int32(s->ZMM_S(3), &env->sse_status);
} }
void helper_cvtpd2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_cvtpd2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); d->ZMM_L(0) = float64_to_int32(s->ZMM_D(0), &env->sse_status);
d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); d->ZMM_L(1) = float64_to_int32(s->ZMM_D(1), &env->sse_status);
d->XMM_Q(1) = 0; d->ZMM_Q(1) = 0;
} }
void helper_cvtps2pi(CPUX86State *env, MMXReg *d, ZMMReg *s) void helper_cvtps2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
{ {
d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); d->MMX_L(0) = float32_to_int32(s->ZMM_S(0), &env->sse_status);
d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); d->MMX_L(1) = float32_to_int32(s->ZMM_S(1), &env->sse_status);
} }
void helper_cvtpd2pi(CPUX86State *env, MMXReg *d, ZMMReg *s) void helper_cvtpd2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
{ {
d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); d->MMX_L(0) = float64_to_int32(s->ZMM_D(0), &env->sse_status);
d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); d->MMX_L(1) = float64_to_int32(s->ZMM_D(1), &env->sse_status);
} }
int32_t helper_cvtss2si(CPUX86State *env, ZMMReg *s) int32_t helper_cvtss2si(CPUX86State *env, ZMMReg *s)
{ {
return float32_to_int32(s->XMM_S(0), &env->sse_status); return float32_to_int32(s->ZMM_S(0), &env->sse_status);
} }
int32_t helper_cvtsd2si(CPUX86State *env, ZMMReg *s) int32_t helper_cvtsd2si(CPUX86State *env, ZMMReg *s)
{ {
return float64_to_int32(s->XMM_D(0), &env->sse_status); return float64_to_int32(s->ZMM_D(0), &env->sse_status);
} }
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
int64_t helper_cvtss2sq(CPUX86State *env, ZMMReg *s) int64_t helper_cvtss2sq(CPUX86State *env, ZMMReg *s)
{ {
return float32_to_int64(s->XMM_S(0), &env->sse_status); return float32_to_int64(s->ZMM_S(0), &env->sse_status);
} }
int64_t helper_cvtsd2sq(CPUX86State *env, ZMMReg *s) int64_t helper_cvtsd2sq(CPUX86State *env, ZMMReg *s)
{ {
return float64_to_int64(s->XMM_D(0), &env->sse_status); return float64_to_int64(s->ZMM_D(0), &env->sse_status);
} }
#endif #endif
/* float to integer truncated */ /* float to integer truncated */
void helper_cvttps2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_cvttps2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); d->ZMM_L(0) = float32_to_int32_round_to_zero(s->ZMM_S(0), &env->sse_status);
d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); d->ZMM_L(1) = float32_to_int32_round_to_zero(s->ZMM_S(1), &env->sse_status);
d->XMM_L(2) = float32_to_int32_round_to_zero(s->XMM_S(2), &env->sse_status); d->ZMM_L(2) = float32_to_int32_round_to_zero(s->ZMM_S(2), &env->sse_status);
d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status); d->ZMM_L(3) = float32_to_int32_round_to_zero(s->ZMM_S(3), &env->sse_status);
} }
void helper_cvttpd2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_cvttpd2dq(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); d->ZMM_L(0) = float64_to_int32_round_to_zero(s->ZMM_D(0), &env->sse_status);
d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); d->ZMM_L(1) = float64_to_int32_round_to_zero(s->ZMM_D(1), &env->sse_status);
d->XMM_Q(1) = 0; d->ZMM_Q(1) = 0;
} }
void helper_cvttps2pi(CPUX86State *env, MMXReg *d, ZMMReg *s) void helper_cvttps2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
{ {
d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); d->MMX_L(0) = float32_to_int32_round_to_zero(s->ZMM_S(0), &env->sse_status);
d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); d->MMX_L(1) = float32_to_int32_round_to_zero(s->ZMM_S(1), &env->sse_status);
} }
void helper_cvttpd2pi(CPUX86State *env, MMXReg *d, ZMMReg *s) void helper_cvttpd2pi(CPUX86State *env, MMXReg *d, ZMMReg *s)
{ {
d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); d->MMX_L(0) = float64_to_int32_round_to_zero(s->ZMM_D(0), &env->sse_status);
d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); d->MMX_L(1) = float64_to_int32_round_to_zero(s->ZMM_D(1), &env->sse_status);
} }
int32_t helper_cvttss2si(CPUX86State *env, ZMMReg *s) int32_t helper_cvttss2si(CPUX86State *env, ZMMReg *s)
{ {
return float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); return float32_to_int32_round_to_zero(s->ZMM_S(0), &env->sse_status);
} }
int32_t helper_cvttsd2si(CPUX86State *env, ZMMReg *s) int32_t helper_cvttsd2si(CPUX86State *env, ZMMReg *s)
{ {
return float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); return float64_to_int32_round_to_zero(s->ZMM_D(0), &env->sse_status);
} }
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
int64_t helper_cvttss2sq(CPUX86State *env, ZMMReg *s) int64_t helper_cvttss2sq(CPUX86State *env, ZMMReg *s)
{ {
return float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status); return float32_to_int64_round_to_zero(s->ZMM_S(0), &env->sse_status);
} }
int64_t helper_cvttsd2sq(CPUX86State *env, ZMMReg *s) int64_t helper_cvttsd2sq(CPUX86State *env, ZMMReg *s)
{ {
return float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status); return float64_to_int64_round_to_zero(s->ZMM_D(0), &env->sse_status);
} }
#endif #endif
void helper_rsqrtps(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_rsqrtps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_S(0) = float32_div(float32_one, d->ZMM_S(0) = float32_div(float32_one,
float32_sqrt(s->XMM_S(0), &env->sse_status), float32_sqrt(s->ZMM_S(0), &env->sse_status),
&env->sse_status); &env->sse_status);
d->XMM_S(1) = float32_div(float32_one, d->ZMM_S(1) = float32_div(float32_one,
float32_sqrt(s->XMM_S(1), &env->sse_status), float32_sqrt(s->ZMM_S(1), &env->sse_status),
&env->sse_status); &env->sse_status);
d->XMM_S(2) = float32_div(float32_one, d->ZMM_S(2) = float32_div(float32_one,
float32_sqrt(s->XMM_S(2), &env->sse_status), float32_sqrt(s->ZMM_S(2), &env->sse_status),
&env->sse_status); &env->sse_status);
d->XMM_S(3) = float32_div(float32_one, d->ZMM_S(3) = float32_div(float32_one,
float32_sqrt(s->XMM_S(3), &env->sse_status), float32_sqrt(s->ZMM_S(3), &env->sse_status),
&env->sse_status); &env->sse_status);
} }
void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_rsqrtss(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_S(0) = float32_div(float32_one, d->ZMM_S(0) = float32_div(float32_one,
float32_sqrt(s->XMM_S(0), &env->sse_status), float32_sqrt(s->ZMM_S(0), &env->sse_status),
&env->sse_status); &env->sse_status);
} }
void helper_rcpps(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_rcpps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status); d->ZMM_S(0) = float32_div(float32_one, s->ZMM_S(0), &env->sse_status);
d->XMM_S(1) = float32_div(float32_one, s->XMM_S(1), &env->sse_status); d->ZMM_S(1) = float32_div(float32_one, s->ZMM_S(1), &env->sse_status);
d->XMM_S(2) = float32_div(float32_one, s->XMM_S(2), &env->sse_status); d->ZMM_S(2) = float32_div(float32_one, s->ZMM_S(2), &env->sse_status);
d->XMM_S(3) = float32_div(float32_one, s->XMM_S(3), &env->sse_status); d->ZMM_S(3) = float32_div(float32_one, s->ZMM_S(3), &env->sse_status);
} }
void helper_rcpss(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_rcpss(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status); d->ZMM_S(0) = float32_div(float32_one, s->ZMM_S(0), &env->sse_status);
} }
static inline uint64_t helper_extrq(uint64_t src, int shift, int len) static inline uint64_t helper_extrq(uint64_t src, int shift, int len)
...@@ -859,12 +859,12 @@ static inline uint64_t helper_extrq(uint64_t src, int shift, int len) ...@@ -859,12 +859,12 @@ static inline uint64_t helper_extrq(uint64_t src, int shift, int len)
void helper_extrq_r(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_extrq_r(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), s->XMM_B(1), s->XMM_B(0)); d->ZMM_Q(0) = helper_extrq(d->ZMM_Q(0), s->ZMM_B(1), s->ZMM_B(0));
} }
void helper_extrq_i(CPUX86State *env, ZMMReg *d, int index, int length) void helper_extrq_i(CPUX86State *env, ZMMReg *d, int index, int length)
{ {
d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), index, length); d->ZMM_Q(0) = helper_extrq(d->ZMM_Q(0), index, length);
} }
static inline uint64_t helper_insertq(uint64_t src, int shift, int len) static inline uint64_t helper_insertq(uint64_t src, int shift, int len)
...@@ -881,22 +881,22 @@ static inline uint64_t helper_insertq(uint64_t src, int shift, int len) ...@@ -881,22 +881,22 @@ static inline uint64_t helper_insertq(uint64_t src, int shift, int len)
void helper_insertq_r(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_insertq_r(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_Q(0) = helper_insertq(s->XMM_Q(0), s->XMM_B(9), s->XMM_B(8)); d->ZMM_Q(0) = helper_insertq(s->ZMM_Q(0), s->ZMM_B(9), s->ZMM_B(8));
} }
void helper_insertq_i(CPUX86State *env, ZMMReg *d, int index, int length) void helper_insertq_i(CPUX86State *env, ZMMReg *d, int index, int length)
{ {
d->XMM_Q(0) = helper_insertq(d->XMM_Q(0), index, length); d->ZMM_Q(0) = helper_insertq(d->ZMM_Q(0), index, length);
} }
void helper_haddps(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_haddps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
ZMMReg r; ZMMReg r;
r.XMM_S(0) = float32_add(d->XMM_S(0), d->XMM_S(1), &env->sse_status); r.ZMM_S(0) = float32_add(d->ZMM_S(0), d->ZMM_S(1), &env->sse_status);
r.XMM_S(1) = float32_add(d->XMM_S(2), d->XMM_S(3), &env->sse_status); r.ZMM_S(1) = float32_add(d->ZMM_S(2), d->ZMM_S(3), &env->sse_status);
r.XMM_S(2) = float32_add(s->XMM_S(0), s->XMM_S(1), &env->sse_status); r.ZMM_S(2) = float32_add(s->ZMM_S(0), s->ZMM_S(1), &env->sse_status);
r.XMM_S(3) = float32_add(s->XMM_S(2), s->XMM_S(3), &env->sse_status); r.ZMM_S(3) = float32_add(s->ZMM_S(2), s->ZMM_S(3), &env->sse_status);
*d = r; *d = r;
} }
...@@ -904,8 +904,8 @@ void helper_haddpd(CPUX86State *env, ZMMReg *d, ZMMReg *s) ...@@ -904,8 +904,8 @@ void helper_haddpd(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
ZMMReg r; ZMMReg r;
r.XMM_D(0) = float64_add(d->XMM_D(0), d->XMM_D(1), &env->sse_status); r.ZMM_D(0) = float64_add(d->ZMM_D(0), d->ZMM_D(1), &env->sse_status);
r.XMM_D(1) = float64_add(s->XMM_D(0), s->XMM_D(1), &env->sse_status); r.ZMM_D(1) = float64_add(s->ZMM_D(0), s->ZMM_D(1), &env->sse_status);
*d = r; *d = r;
} }
...@@ -913,10 +913,10 @@ void helper_hsubps(CPUX86State *env, ZMMReg *d, ZMMReg *s) ...@@ -913,10 +913,10 @@ void helper_hsubps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
ZMMReg r; ZMMReg r;
r.XMM_S(0) = float32_sub(d->XMM_S(0), d->XMM_S(1), &env->sse_status); r.ZMM_S(0) = float32_sub(d->ZMM_S(0), d->ZMM_S(1), &env->sse_status);
r.XMM_S(1) = float32_sub(d->XMM_S(2), d->XMM_S(3), &env->sse_status); r.ZMM_S(1) = float32_sub(d->ZMM_S(2), d->ZMM_S(3), &env->sse_status);
r.XMM_S(2) = float32_sub(s->XMM_S(0), s->XMM_S(1), &env->sse_status); r.ZMM_S(2) = float32_sub(s->ZMM_S(0), s->ZMM_S(1), &env->sse_status);
r.XMM_S(3) = float32_sub(s->XMM_S(2), s->XMM_S(3), &env->sse_status); r.ZMM_S(3) = float32_sub(s->ZMM_S(2), s->ZMM_S(3), &env->sse_status);
*d = r; *d = r;
} }
...@@ -924,49 +924,49 @@ void helper_hsubpd(CPUX86State *env, ZMMReg *d, ZMMReg *s) ...@@ -924,49 +924,49 @@ void helper_hsubpd(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
ZMMReg r; ZMMReg r;
r.XMM_D(0) = float64_sub(d->XMM_D(0), d->XMM_D(1), &env->sse_status); r.ZMM_D(0) = float64_sub(d->ZMM_D(0), d->ZMM_D(1), &env->sse_status);
r.XMM_D(1) = float64_sub(s->XMM_D(0), s->XMM_D(1), &env->sse_status); r.ZMM_D(1) = float64_sub(s->ZMM_D(0), s->ZMM_D(1), &env->sse_status);
*d = r; *d = r;
} }
void helper_addsubps(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_addsubps(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_S(0) = float32_sub(d->XMM_S(0), s->XMM_S(0), &env->sse_status); d->ZMM_S(0) = float32_sub(d->ZMM_S(0), s->ZMM_S(0), &env->sse_status);
d->XMM_S(1) = float32_add(d->XMM_S(1), s->XMM_S(1), &env->sse_status); d->ZMM_S(1) = float32_add(d->ZMM_S(1), s->ZMM_S(1), &env->sse_status);
d->XMM_S(2) = float32_sub(d->XMM_S(2), s->XMM_S(2), &env->sse_status); d->ZMM_S(2) = float32_sub(d->ZMM_S(2), s->ZMM_S(2), &env->sse_status);
d->XMM_S(3) = float32_add(d->XMM_S(3), s->XMM_S(3), &env->sse_status); d->ZMM_S(3) = float32_add(d->ZMM_S(3), s->ZMM_S(3), &env->sse_status);
} }
void helper_addsubpd(CPUX86State *env, ZMMReg *d, ZMMReg *s) void helper_addsubpd(CPUX86State *env, ZMMReg *d, ZMMReg *s)
{ {
d->XMM_D(0) = float64_sub(d->XMM_D(0), s->XMM_D(0), &env->sse_status); d->ZMM_D(0) = float64_sub(d->ZMM_D(0), s->ZMM_D(0), &env->sse_status);
d->XMM_D(1) = float64_add(d->XMM_D(1), s->XMM_D(1), &env->sse_status); d->ZMM_D(1) = float64_add(d->ZMM_D(1), s->ZMM_D(1), &env->sse_status);
} }
/* XXX: unordered */ /* XXX: unordered */
#define SSE_HELPER_CMP(name, F) \ #define SSE_HELPER_CMP(name, F) \
void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \ void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \
{ \ { \
d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ d->ZMM_L(0) = F(32, d->ZMM_S(0), s->ZMM_S(0)); \
d->XMM_L(1) = F(32, d->XMM_S(1), s->XMM_S(1)); \ d->ZMM_L(1) = F(32, d->ZMM_S(1), s->ZMM_S(1)); \
d->XMM_L(2) = F(32, d->XMM_S(2), s->XMM_S(2)); \ d->ZMM_L(2) = F(32, d->ZMM_S(2), s->ZMM_S(2)); \
d->XMM_L(3) = F(32, d->XMM_S(3), s->XMM_S(3)); \ d->ZMM_L(3) = F(32, d->ZMM_S(3), s->ZMM_S(3)); \
} \ } \
\ \
void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \ void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \
{ \ { \
d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ d->ZMM_L(0) = F(32, d->ZMM_S(0), s->ZMM_S(0)); \
} \ } \
\ \
void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \ void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \
{ \ { \
d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ d->ZMM_Q(0) = F(64, d->ZMM_D(0), s->ZMM_D(0)); \
d->XMM_Q(1) = F(64, d->XMM_D(1), s->XMM_D(1)); \ d->ZMM_Q(1) = F(64, d->ZMM_D(1), s->ZMM_D(1)); \
} \ } \
\ \
void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \ void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \
{ \ { \
d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ d->ZMM_Q(0) = F(64, d->ZMM_D(0), s->ZMM_D(0)); \
} }
#define FPU_CMPEQ(size, a, b) \ #define FPU_CMPEQ(size, a, b) \
...@@ -1002,8 +1002,8 @@ void helper_ucomiss(CPUX86State *env, Reg *d, Reg *s) ...@@ -1002,8 +1002,8 @@ void helper_ucomiss(CPUX86State *env, Reg *d, Reg *s)
int ret; int ret;
float32 s0, s1; float32 s0, s1;
s0 = d->XMM_S(0); s0 = d->ZMM_S(0);
s1 = s->XMM_S(0); s1 = s->ZMM_S(0);
ret = float32_compare_quiet(s0, s1, &env->sse_status); ret = float32_compare_quiet(s0, s1, &env->sse_status);
CC_SRC = comis_eflags[ret + 1]; CC_SRC = comis_eflags[ret + 1];
} }
...@@ -1013,8 +1013,8 @@ void helper_comiss(CPUX86State *env, Reg *d, Reg *s) ...@@ -1013,8 +1013,8 @@ void helper_comiss(CPUX86State *env, Reg *d, Reg *s)
int ret; int ret;
float32 s0, s1; float32 s0, s1;
s0 = d->XMM_S(0); s0 = d->ZMM_S(0);
s1 = s->XMM_S(0); s1 = s->ZMM_S(0);
ret = float32_compare(s0, s1, &env->sse_status); ret = float32_compare(s0, s1, &env->sse_status);
CC_SRC = comis_eflags[ret + 1]; CC_SRC = comis_eflags[ret + 1];
} }
...@@ -1024,8 +1024,8 @@ void helper_ucomisd(CPUX86State *env, Reg *d, Reg *s) ...@@ -1024,8 +1024,8 @@ void helper_ucomisd(CPUX86State *env, Reg *d, Reg *s)
int ret; int ret;
float64 d0, d1; float64 d0, d1;
d0 = d->XMM_D(0); d0 = d->ZMM_D(0);
d1 = s->XMM_D(0); d1 = s->ZMM_D(0);
ret = float64_compare_quiet(d0, d1, &env->sse_status); ret = float64_compare_quiet(d0, d1, &env->sse_status);
CC_SRC = comis_eflags[ret + 1]; CC_SRC = comis_eflags[ret + 1];
} }
...@@ -1035,8 +1035,8 @@ void helper_comisd(CPUX86State *env, Reg *d, Reg *s) ...@@ -1035,8 +1035,8 @@ void helper_comisd(CPUX86State *env, Reg *d, Reg *s)
int ret; int ret;
float64 d0, d1; float64 d0, d1;
d0 = d->XMM_D(0); d0 = d->ZMM_D(0);
d1 = s->XMM_D(0); d1 = s->ZMM_D(0);
ret = float64_compare(d0, d1, &env->sse_status); ret = float64_compare(d0, d1, &env->sse_status);
CC_SRC = comis_eflags[ret + 1]; CC_SRC = comis_eflags[ret + 1];
} }
...@@ -1045,10 +1045,10 @@ uint32_t helper_movmskps(CPUX86State *env, Reg *s) ...@@ -1045,10 +1045,10 @@ uint32_t helper_movmskps(CPUX86State *env, Reg *s)
{ {
int b0, b1, b2, b3; int b0, b1, b2, b3;
b0 = s->XMM_L(0) >> 31; b0 = s->ZMM_L(0) >> 31;
b1 = s->XMM_L(1) >> 31; b1 = s->ZMM_L(1) >> 31;
b2 = s->XMM_L(2) >> 31; b2 = s->ZMM_L(2) >> 31;
b3 = s->XMM_L(3) >> 31; b3 = s->ZMM_L(3) >> 31;
return b0 | (b1 << 1) | (b2 << 2) | (b3 << 3); return b0 | (b1 << 1) | (b2 << 2) | (b3 << 3);
} }
...@@ -1056,8 +1056,8 @@ uint32_t helper_movmskpd(CPUX86State *env, Reg *s) ...@@ -1056,8 +1056,8 @@ uint32_t helper_movmskpd(CPUX86State *env, Reg *s)
{ {
int b0, b1; int b0, b1;
b0 = s->XMM_L(1) >> 31; b0 = s->ZMM_L(1) >> 31;
b1 = s->XMM_L(3) >> 31; b1 = s->ZMM_L(3) >> 31;
return b0 | (b1 << 1); return b0 | (b1 << 1);
} }
...@@ -1736,10 +1736,10 @@ void glue(helper_roundps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, ...@@ -1736,10 +1736,10 @@ void glue(helper_roundps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
} }
} }
d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status); d->ZMM_S(0) = float32_round_to_int(s->ZMM_S(0), &env->sse_status);
d->XMM_S(1) = float32_round_to_int(s->XMM_S(1), &env->sse_status); d->ZMM_S(1) = float32_round_to_int(s->ZMM_S(1), &env->sse_status);
d->XMM_S(2) = float32_round_to_int(s->XMM_S(2), &env->sse_status); d->ZMM_S(2) = float32_round_to_int(s->ZMM_S(2), &env->sse_status);
d->XMM_S(3) = float32_round_to_int(s->XMM_S(3), &env->sse_status); d->ZMM_S(3) = float32_round_to_int(s->ZMM_S(3), &env->sse_status);
#if 0 /* TODO */ #if 0 /* TODO */
if (mode & (1 << 3)) { if (mode & (1 << 3)) {
...@@ -1774,8 +1774,8 @@ void glue(helper_roundpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, ...@@ -1774,8 +1774,8 @@ void glue(helper_roundpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
} }
} }
d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status); d->ZMM_D(0) = float64_round_to_int(s->ZMM_D(0), &env->sse_status);
d->XMM_D(1) = float64_round_to_int(s->XMM_D(1), &env->sse_status); d->ZMM_D(1) = float64_round_to_int(s->ZMM_D(1), &env->sse_status);
#if 0 /* TODO */ #if 0 /* TODO */
if (mode & (1 << 3)) { if (mode & (1 << 3)) {
...@@ -1810,7 +1810,7 @@ void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, ...@@ -1810,7 +1810,7 @@ void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
} }
} }
d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status); d->ZMM_S(0) = float32_round_to_int(s->ZMM_S(0), &env->sse_status);
#if 0 /* TODO */ #if 0 /* TODO */
if (mode & (1 << 3)) { if (mode & (1 << 3)) {
...@@ -1845,7 +1845,7 @@ void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, ...@@ -1845,7 +1845,7 @@ void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
} }
} }
d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status); d->ZMM_D(0) = float64_round_to_int(s->ZMM_D(0), &env->sse_status);
#if 0 /* TODO */ #if 0 /* TODO */
if (mode & (1 << 3)) { if (mode & (1 << 3)) {
...@@ -1868,32 +1868,32 @@ void glue(helper_dpps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask) ...@@ -1868,32 +1868,32 @@ void glue(helper_dpps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask)
if (mask & (1 << 4)) { if (mask & (1 << 4)) {
iresult = float32_add(iresult, iresult = float32_add(iresult,
float32_mul(d->XMM_S(0), s->XMM_S(0), float32_mul(d->ZMM_S(0), s->ZMM_S(0),
&env->sse_status), &env->sse_status),
&env->sse_status); &env->sse_status);
} }
if (mask & (1 << 5)) { if (mask & (1 << 5)) {
iresult = float32_add(iresult, iresult = float32_add(iresult,
float32_mul(d->XMM_S(1), s->XMM_S(1), float32_mul(d->ZMM_S(1), s->ZMM_S(1),
&env->sse_status), &env->sse_status),
&env->sse_status); &env->sse_status);
} }
if (mask & (1 << 6)) { if (mask & (1 << 6)) {
iresult = float32_add(iresult, iresult = float32_add(iresult,
float32_mul(d->XMM_S(2), s->XMM_S(2), float32_mul(d->ZMM_S(2), s->ZMM_S(2),
&env->sse_status), &env->sse_status),
&env->sse_status); &env->sse_status);
} }
if (mask & (1 << 7)) { if (mask & (1 << 7)) {
iresult = float32_add(iresult, iresult = float32_add(iresult,
float32_mul(d->XMM_S(3), s->XMM_S(3), float32_mul(d->ZMM_S(3), s->ZMM_S(3),
&env->sse_status), &env->sse_status),
&env->sse_status); &env->sse_status);
} }
d->XMM_S(0) = (mask & (1 << 0)) ? iresult : float32_zero; d->ZMM_S(0) = (mask & (1 << 0)) ? iresult : float32_zero;
d->XMM_S(1) = (mask & (1 << 1)) ? iresult : float32_zero; d->ZMM_S(1) = (mask & (1 << 1)) ? iresult : float32_zero;
d->XMM_S(2) = (mask & (1 << 2)) ? iresult : float32_zero; d->ZMM_S(2) = (mask & (1 << 2)) ? iresult : float32_zero;
d->XMM_S(3) = (mask & (1 << 3)) ? iresult : float32_zero; d->ZMM_S(3) = (mask & (1 << 3)) ? iresult : float32_zero;
} }
void glue(helper_dppd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask) void glue(helper_dppd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask)
...@@ -1902,18 +1902,18 @@ void glue(helper_dppd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask) ...@@ -1902,18 +1902,18 @@ void glue(helper_dppd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask)
if (mask & (1 << 4)) { if (mask & (1 << 4)) {
iresult = float64_add(iresult, iresult = float64_add(iresult,
float64_mul(d->XMM_D(0), s->XMM_D(0), float64_mul(d->ZMM_D(0), s->ZMM_D(0),
&env->sse_status), &env->sse_status),
&env->sse_status); &env->sse_status);
} }
if (mask & (1 << 5)) { if (mask & (1 << 5)) {
iresult = float64_add(iresult, iresult = float64_add(iresult,
float64_mul(d->XMM_D(1), s->XMM_D(1), float64_mul(d->ZMM_D(1), s->ZMM_D(1),
&env->sse_status), &env->sse_status),
&env->sse_status); &env->sse_status);
} }
d->XMM_D(0) = (mask & (1 << 0)) ? iresult : float64_zero; d->ZMM_D(0) = (mask & (1 << 0)) ? iresult : float64_zero;
d->XMM_D(1) = (mask & (1 << 1)) ? iresult : float64_zero; d->ZMM_D(1) = (mask & (1 << 1)) ? iresult : float64_zero;
} }
void glue(helper_mpsadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, void glue(helper_mpsadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
......
target-i386/translate.c
浏览文件 @ 19cbd87c
...@@ -2602,28 +2602,28 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset) ...@@ -2602,28 +2602,28 @@ static inline void gen_ldo_env_A0(DisasContext *s, int offset)
{ {
int mem_index = s->mem_index; int mem_index = s->mem_index;
tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ); tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, XMM_Q(0))); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ); tcg_gen_qemu_ld_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, XMM_Q(1))); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
} }
static inline void gen_sto_env_A0(DisasContext *s, int offset) static inline void gen_sto_env_A0(DisasContext *s, int offset)
{ {
int mem_index = s->mem_index; int mem_index = s->mem_index;
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, XMM_Q(0))); tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ); tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, XMM_Q(1))); tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ); tcg_gen_qemu_st_i64(cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
} }
static inline void gen_op_movo(int d_offset, int s_offset) static inline void gen_op_movo(int d_offset, int s_offset)
{ {
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + offsetof(ZMMReg, XMM_Q(0))); tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + offsetof(ZMMReg, ZMM_Q(0)));
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + offsetof(ZMMReg, XMM_Q(0))); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + offsetof(ZMMReg, ZMM_Q(0)));
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + offsetof(ZMMReg, XMM_Q(1))); tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + offsetof(ZMMReg, ZMM_Q(1)));
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + offsetof(ZMMReg, XMM_Q(1))); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + offsetof(ZMMReg, ZMM_Q(1)));
} }
static inline void gen_op_movq(int d_offset, int s_offset) static inline void gen_op_movq(int d_offset, int s_offset)
...@@ -3074,10 +3074,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3074,10 +3074,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
if (b1 & 1) { if (b1 & 1) {
gen_stq_env_A0(s, offsetof(CPUX86State, gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0))); xmm_regs[reg].ZMM_Q(0)));
} else { } else {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(0))); xmm_regs[reg].ZMM_L(0)));
gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
} }
break; break;
...@@ -3144,29 +3144,29 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3144,29 +3144,29 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));
tcg_gen_movi_tl(cpu_T[0], 0); tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(1)));
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2)));
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3)));
} else { } else {
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)),
offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); offsetof(CPUX86State,xmm_regs[rm].ZMM_L(0)));
} }
break; break;
case 0x310: /* movsd xmm, ea */ case 0x310: /* movsd xmm, ea */
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State, gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0))); xmm_regs[reg].ZMM_Q(0)));
tcg_gen_movi_tl(cpu_T[0], 0); tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2)));
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3)));
} else { } else {
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)),
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)));
} }
break; break;
case 0x012: /* movlps */ case 0x012: /* movlps */
...@@ -3174,12 +3174,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3174,12 +3174,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State, gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0))); xmm_regs[reg].ZMM_Q(0)));
} else { } else {
/* movhlps */ /* movhlps */
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)),
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(1)));
} }
break; break;
case 0x212: /* movsldup */ case 0x212: /* movsldup */
...@@ -3188,40 +3188,40 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3188,40 +3188,40 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else { } else {
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)),
offsetof(CPUX86State,xmm_regs[rm].XMM_L(0))); offsetof(CPUX86State,xmm_regs[rm].ZMM_L(0)));
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2)),
offsetof(CPUX86State,xmm_regs[rm].XMM_L(2))); offsetof(CPUX86State,xmm_regs[rm].ZMM_L(2)));
} }
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].ZMM_L(1)),
offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3)),
offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2)));
break; break;
case 0x312: /* movddup */ case 0x312: /* movddup */
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State, gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0))); xmm_regs[reg].ZMM_Q(0)));
} else { } else {
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)),
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)));
} }
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(1)),
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)));
break; break;
case 0x016: /* movhps */ case 0x016: /* movhps */
case 0x116: /* movhpd */ case 0x116: /* movhpd */
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State, gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(1))); xmm_regs[reg].ZMM_Q(1)));
} else { } else {
/* movlhps */ /* movlhps */
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)), gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(1)),
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)));
} }
break; break;
case 0x216: /* movshdup */ case 0x216: /* movshdup */
...@@ -3230,15 +3230,15 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3230,15 +3230,15 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg]));
} else { } else {
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].ZMM_L(1)),
offsetof(CPUX86State,xmm_regs[rm].XMM_L(1))); offsetof(CPUX86State,xmm_regs[rm].ZMM_L(1)));
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)), gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3)),
offsetof(CPUX86State,xmm_regs[rm].XMM_L(3))); offsetof(CPUX86State,xmm_regs[rm].ZMM_L(3)));
} }
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)),
offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); offsetof(CPUX86State,xmm_regs[reg].ZMM_L(1)));
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)), gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].ZMM_L(2)),
offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); offsetof(CPUX86State,xmm_regs[reg].ZMM_L(3)));
break; break;
case 0x178: case 0x178:
case 0x378: case 0x378:
...@@ -3279,13 +3279,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3279,13 +3279,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
if (s->dflag == MO_64) { if (s->dflag == MO_64) {
tcg_gen_ld_i64(cpu_T[0], cpu_env, tcg_gen_ld_i64(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)));
gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1); gen_ldst_modrm(env, s, modrm, MO_64, OR_TMP0, 1);
} else } else
#endif #endif
{ {
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));
gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1); gen_ldst_modrm(env, s, modrm, MO_32, OR_TMP0, 1);
} }
break; break;
...@@ -3293,13 +3293,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3293,13 +3293,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, offsetof(CPUX86State, gen_ldq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0))); xmm_regs[reg].ZMM_Q(0)));
} else { } else {
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)),
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)));
} }
gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(1)));
break; break;
case 0x7f: /* movq ea, mm */ case 0x7f: /* movq ea, mm */
if (mod != 3) { if (mod != 3) {
...@@ -3329,23 +3329,23 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3329,23 +3329,23 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x211: /* movss ea, xmm */ case 0x211: /* movss ea, xmm */
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));
gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0);
} else { } else {
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].ZMM_L(0)),
offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); offsetof(CPUX86State,xmm_regs[reg].ZMM_L(0)));
} }
break; break;
case 0x311: /* movsd ea, xmm */ case 0x311: /* movsd ea, xmm */
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State, gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0))); xmm_regs[reg].ZMM_Q(0)));
} else { } else {
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)),
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)));
} }
break; break;
case 0x013: /* movlps */ case 0x013: /* movlps */
...@@ -3353,7 +3353,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3353,7 +3353,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State, gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0))); xmm_regs[reg].ZMM_Q(0)));
} else { } else {
goto illegal_op; goto illegal_op;
} }
...@@ -3363,7 +3363,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3363,7 +3363,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State, gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(1))); xmm_regs[reg].ZMM_Q(1)));
} else { } else {
goto illegal_op; goto illegal_op;
} }
...@@ -3380,9 +3380,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3380,9 +3380,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
val = cpu_ldub_code(env, s->pc++); val = cpu_ldub_code(env, s->pc++);
if (is_xmm) { if (is_xmm) {
tcg_gen_movi_tl(cpu_T[0], val); tcg_gen_movi_tl(cpu_T[0], val);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(0)));
tcg_gen_movi_tl(cpu_T[0], 0); tcg_gen_movi_tl(cpu_T[0], 0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(1)));
op1_offset = offsetof(CPUX86State,xmm_t0); op1_offset = offsetof(CPUX86State,xmm_t0);
} else { } else {
tcg_gen_movi_tl(cpu_T[0], val); tcg_gen_movi_tl(cpu_T[0], val);
...@@ -3503,10 +3503,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3503,10 +3503,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
if ((b >> 8) & 1) { if ((b >> 8) & 1) {
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0))); gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.ZMM_Q(0)));
} else { } else {
gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.ZMM_L(0)));
} }
op2_offset = offsetof(CPUX86State,xmm_t0); op2_offset = offsetof(CPUX86State,xmm_t0);
} else { } else {
...@@ -3538,7 +3538,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3538,7 +3538,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (b1) { if (b1) {
val &= 7; val &= 7;
tcg_gen_st16_tl(cpu_T[0], cpu_env, tcg_gen_st16_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[reg].XMM_W(val))); offsetof(CPUX86State,xmm_regs[reg].ZMM_W(val)));
} else { } else {
val &= 3; val &= 3;
tcg_gen_st16_tl(cpu_T[0], cpu_env, tcg_gen_st16_tl(cpu_T[0], cpu_env,
...@@ -3555,7 +3555,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3555,7 +3555,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
val &= 7; val &= 7;
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_regs[rm].XMM_W(val))); offsetof(CPUX86State,xmm_regs[rm].ZMM_W(val)));
} else { } else {
val &= 3; val &= 3;
rm = (modrm & 7); rm = (modrm & 7);
...@@ -3569,26 +3569,26 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3569,26 +3569,26 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod != 3) { if (mod != 3) {
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_stq_env_A0(s, offsetof(CPUX86State, gen_stq_env_A0(s, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(0))); xmm_regs[reg].ZMM_Q(0)));
} else { } else {
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)),
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)));
gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1))); gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(1)));
} }
break; break;
case 0x2d6: /* movq2dq */ case 0x2d6: /* movq2dq */
gen_helper_enter_mmx(cpu_env); gen_helper_enter_mmx(cpu_env);
rm = (modrm & 7); rm = (modrm & 7);
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(0)),
offsetof(CPUX86State,fpregs[rm].mmx)); offsetof(CPUX86State,fpregs[rm].mmx));
gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].ZMM_Q(1)));
break; break;
case 0x3d6: /* movdq2q */ case 0x3d6: /* movdq2q */
gen_helper_enter_mmx(cpu_env); gen_helper_enter_mmx(cpu_env);
rm = (modrm & 7) | REX_B(s); rm = (modrm & 7) | REX_B(s);
gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx), gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0))); offsetof(CPUX86State,xmm_regs[rm].ZMM_Q(0)));
break; break;
case 0xd7: /* pmovmskb */ case 0xd7: /* pmovmskb */
case 0x1d7: case 0x1d7:
...@@ -3640,20 +3640,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -3640,20 +3640,20 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
gen_ldq_env_A0(s, op2_offset + gen_ldq_env_A0(s, op2_offset +
offsetof(ZMMReg, XMM_Q(0))); offsetof(ZMMReg, ZMM_Q(0)));
break; break;
case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */ case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
s->mem_index, MO_LEUL); s->mem_index, MO_LEUL);
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset + tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
offsetof(ZMMReg, XMM_L(0))); offsetof(ZMMReg, ZMM_L(0)));
break; break;
case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */ case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0, tcg_gen_qemu_ld_tl(cpu_tmp0, cpu_A0,
s->mem_index, MO_LEUW); s->mem_index, MO_LEUW);
tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset + tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
offsetof(ZMMReg, XMM_W(0))); offsetof(ZMMReg, ZMM_W(0)));
break; break;
case 0x2a: /* movntqda */ case 0x2a: /* movntqda */
gen_ldo_env_A0(s, op1_offset); gen_ldo_env_A0(s, op1_offset);
...@@ -4078,7 +4078,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -4078,7 +4078,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
switch (b) { switch (b) {
case 0x14: /* pextrb */ case 0x14: /* pextrb */
tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15))); xmm_regs[reg].ZMM_B(val & 15)));
if (mod == 3) { if (mod == 3) {
gen_op_mov_reg_v(ot, rm, cpu_T[0]); gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else { } else {
...@@ -4088,7 +4088,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -4088,7 +4088,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break; break;
case 0x15: /* pextrw */ case 0x15: /* pextrw */
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_W(val & 7))); xmm_regs[reg].ZMM_W(val & 7)));
if (mod == 3) { if (mod == 3) {
gen_op_mov_reg_v(ot, rm, cpu_T[0]); gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else { } else {
...@@ -4100,7 +4100,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -4100,7 +4100,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (ot == MO_32) { /* pextrd */ if (ot == MO_32) { /* pextrd */
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3))); xmm_regs[reg].ZMM_L(val & 3)));
if (mod == 3) { if (mod == 3) {
tcg_gen_extu_i32_tl(cpu_regs[rm], cpu_tmp2_i32); tcg_gen_extu_i32_tl(cpu_regs[rm], cpu_tmp2_i32);
} else { } else {
...@@ -4111,7 +4111,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -4111,7 +4111,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
offsetof(CPUX86State, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1))); xmm_regs[reg].ZMM_Q(val & 1)));
if (mod == 3) { if (mod == 3) {
tcg_gen_mov_i64(cpu_regs[rm], cpu_tmp1_i64); tcg_gen_mov_i64(cpu_regs[rm], cpu_tmp1_i64);
} else { } else {
...@@ -4125,7 +4125,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -4125,7 +4125,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break; break;
case 0x17: /* extractps */ case 0x17: /* extractps */
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3))); xmm_regs[reg].ZMM_L(val & 3)));
if (mod == 3) { if (mod == 3) {
gen_op_mov_reg_v(ot, rm, cpu_T[0]); gen_op_mov_reg_v(ot, rm, cpu_T[0]);
} else { } else {
...@@ -4141,36 +4141,36 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -4141,36 +4141,36 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
s->mem_index, MO_UB); s->mem_index, MO_UB);
} }
tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15))); xmm_regs[reg].ZMM_B(val & 15)));
break; break;
case 0x21: /* insertps */ case 0x21: /* insertps */
if (mod == 3) { if (mod == 3) {
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,xmm_regs[rm] offsetof(CPUX86State,xmm_regs[rm]
.XMM_L((val >> 6) & 3))); .ZMM_L((val >> 6) & 3)));
} else { } else {
tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0, tcg_gen_qemu_ld_i32(cpu_tmp2_i32, cpu_A0,
s->mem_index, MO_LEUL); s->mem_index, MO_LEUL);
} }
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State,xmm_regs[reg] offsetof(CPUX86State,xmm_regs[reg]
.XMM_L((val >> 4) & 3))); .ZMM_L((val >> 4) & 3)));
if ((val >> 0) & 1) if ((val >> 0) & 1)
tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
cpu_env, offsetof(CPUX86State, cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(0))); xmm_regs[reg].ZMM_L(0)));
if ((val >> 1) & 1) if ((val >> 1) & 1)
tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
cpu_env, offsetof(CPUX86State, cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(1))); xmm_regs[reg].ZMM_L(1)));
if ((val >> 2) & 1) if ((val >> 2) & 1)
tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
cpu_env, offsetof(CPUX86State, cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(2))); xmm_regs[reg].ZMM_L(2)));
if ((val >> 3) & 1) if ((val >> 3) & 1)
tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/), tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
cpu_env, offsetof(CPUX86State, cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(3))); xmm_regs[reg].ZMM_L(3)));
break; break;
case 0x22: case 0x22:
if (ot == MO_32) { /* pinsrd */ if (ot == MO_32) { /* pinsrd */
...@@ -4182,7 +4182,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -4182,7 +4182,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} }
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
offsetof(CPUX86State, offsetof(CPUX86State,
xmm_regs[reg].XMM_L(val & 3))); xmm_regs[reg].ZMM_L(val & 3)));
} else { /* pinsrq */ } else { /* pinsrq */
#ifdef TARGET_X86_64 #ifdef TARGET_X86_64
if (mod == 3) { if (mod == 3) {
...@@ -4193,7 +4193,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -4193,7 +4193,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
} }
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
offsetof(CPUX86State, offsetof(CPUX86State,
xmm_regs[reg].XMM_Q(val & 1))); xmm_regs[reg].ZMM_Q(val & 1)));
#else #else
goto illegal_op; goto illegal_op;
#endif #endif
...@@ -4318,11 +4318,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, ...@@ -4318,11 +4318,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* 32 bit access */ /* 32 bit access */
gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0);
tcg_gen_st32_tl(cpu_T[0], cpu_env, tcg_gen_st32_tl(cpu_T[0], cpu_env,
offsetof(CPUX86State,xmm_t0.XMM_L(0))); offsetof(CPUX86State,xmm_t0.ZMM_L(0)));
break; break;
case 3: case 3:
/* 64 bit access */ /* 64 bit access */
gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_D(0))); gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.ZMM_D(0)));
break; break;
default: default:
/* 128 bit access */ /* 128 bit access */
......
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