Fix RDHWR handling. Code formatting. Don't use *_direct versions to raise

exceptions.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2611 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/op.c

@@ -336,7 +336,7 @@ void op_addo (void)
     T0 = (int32_t)T0 + (int32_t)T1;
     if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
         /* operands of same sign, result different sign */
-        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
+        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
     }
     T0 = (int32_t)T0;
     RETURN();
@@ -356,7 +356,7 @@ void op_subo (void)
     T0 = (int32_t)T0 - (int32_t)T1;
     if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
         /* operands of different sign, first operand and result different sign */
-        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
+        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
     }
     T0 = (int32_t)T0;
     RETURN();
@@ -402,7 +402,7 @@ void op_daddo (void)
     T0 += T1;
     if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
         /* operands of same sign, result different sign */
-        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
+        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
     }
     RETURN();
 }
@@ -421,7 +421,7 @@ void op_dsubo (void)
     T0 = (int64_t)T0 - (int64_t)T1;
     if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
         /* operands of different sign, first operand and result different sign */
-        CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
+        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
     }
     RETURN();
 }
@@ -1650,7 +1650,7 @@ void op_cp0_enabled(void)
 {
     if (!(env->CP0_Status & (1 << CP0St_CU0)) &&
 	(env->hflags & MIPS_HFLAG_UM)) {
-        CALL_FROM_TB2(do_raise_exception_direct_err, EXCP_CpU, 0);
+        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0);
     }
     RETURN();
 }
@@ -1658,7 +1658,7 @@ void op_cp0_enabled(void)
 void op_cp1_enabled(void)
 {
     if (!(env->CP0_Status & (1 << CP0St_CU1))) {
-        CALL_FROM_TB2(do_raise_exception_direct_err, EXCP_CpU, 1);
+        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
     }
     RETURN();
 }
@@ -2063,7 +2063,7 @@ void op_ei (void)
 void op_trap (void)
 {
     if (T0) {
-        CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP);
+        CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);
     }
     RETURN();
 }
@@ -2116,37 +2116,67 @@ void op_deret (void)
 
 void op_rdhwr_cpunum(void)
 {
-    if (env->CP0_HWREna & (1 << 0))
-       T0 = env->CP0_EBase & 0x2ff;
+    if (!(env->hflags & MIPS_HFLAG_UM) ||
+	(env->CP0_HWREna & (1 << 0)) ||
+        (env->CP0_Status & (1 << CP0St_CU0)))
+        T0 = env->CP0_EBase & 0x3ff;
     else
-       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
+        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
     RETURN();
 }
 
 void op_rdhwr_synci_step(void)
 {
-    if (env->CP0_HWREna & (1 << 1))
+    if (!(env->hflags & MIPS_HFLAG_UM) ||
+	(env->CP0_HWREna & (1 << 1)) ||
+        (env->CP0_Status & (1 << CP0St_CU0)))
         T0 = env->SYNCI_Step;
     else
-       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
+        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
     RETURN();
 }
 
 void op_rdhwr_cc(void)
 {
-    if (env->CP0_HWREna & (1 << 2))
+    if (!(env->hflags & MIPS_HFLAG_UM) ||
+	(env->CP0_HWREna & (1 << 2)) ||
+        (env->CP0_Status & (1 << CP0St_CU0)))
         T0 = env->CP0_Count;
     else
-       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
+        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
     RETURN();
 }
 
 void op_rdhwr_ccres(void)
 {
-    if (env->CP0_HWREna & (1 << 3))
+    if (!(env->hflags & MIPS_HFLAG_UM) ||
+	(env->CP0_HWREna & (1 << 3)) ||
+        (env->CP0_Status & (1 << CP0St_CU0)))
         T0 = env->CCRes;
     else
-       CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
+        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
+    RETURN();
+}
+
+void op_rdhwr_unimpl30(void)
+{
+    if (!(env->hflags & MIPS_HFLAG_UM) ||
+	(env->CP0_HWREna & (1 << 30)) ||
+        (env->CP0_Status & (1 << CP0St_CU0)))
+        T0 = 0;
+    else
+        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
+    RETURN();
+}
+
+void op_rdhwr_unimpl31(void)
+{
+    if (!(env->hflags & MIPS_HFLAG_UM) ||
+	(env->CP0_HWREna & (1 << 31)) ||
+        (env->CP0_Status & (1 << CP0St_CU0)))
+        T0 = 0;
+    else
+        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
     RETURN();
 }
 

target-mips/translate.c

@@ -4745,12 +4745,21 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
             case 3:
                 gen_op_rdhwr_ccres();
                 break;
-#if defined (CONFIG_USER_ONLY)
             case 29:
+#if defined (CONFIG_USER_ONLY)
                 gen_op_tls_value ();
-               GEN_STORE_TN_REG(rt, T0);
-               break;
+#else
+                generate_exception(ctx, EXCP_RI);
 #endif
+                break;
+            case 30:
+                /* Implementation dependent */;
+                gen_op_rdhwr_unimpl30();
+                break;
+            case 31:
+                /* Implementation dependent */;
+                gen_op_rdhwr_unimpl31();
+                break;
             default:            /* Invalid */
                 MIPS_INVAL("rdhwr");
                 generate_exception(ctx, EXCP_RI);