From 0208def1cadd4f72f862e62548c2af268a543b20 Mon Sep 17 00:00:00 2001 From: Isaku Yamahata Date: Wed, 20 Oct 2010 17:18:51 +0900 Subject: [PATCH] pci/bridge: fix pci_bridge_reset() The lower bits of base/limit registers is RO and shouldn't be zero cleared on reset. This patch fixes it. In fact, the default value of base/limit registers aren't specified in the spec. And some bridges disable forwarding on reset instead of zeroing base/limit registers. So introduce one function to disable bridge forwarding so that such bridges can use it. It will be used later. Signed-off-by: Isaku Yamahata Signed-off-by: Michael S. Tsirkin --- hw/pci_bridge.c | 48 ++++++++++++++++++++++++++++++++++++++++++------ hw/pci_bridge.h | 1 + 2 files changed, 43 insertions(+), 6 deletions(-) diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c index 638e3b35eb..7e8488a4fb 100644 --- a/hw/pci_bridge.c +++ b/hw/pci_bridge.c @@ -151,6 +151,26 @@ void pci_bridge_write_config(PCIDevice *d, } } +void pci_bridge_disable_base_limit(PCIDevice *dev) +{ + uint8_t *conf = dev->config; + + pci_byte_test_and_set_mask(conf + PCI_IO_BASE, + PCI_IO_RANGE_MASK & 0xff); + pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, + PCI_IO_RANGE_MASK & 0xff); + pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE, + PCI_PREF_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, + PCI_PREF_RANGE_MASK & 0xffff); + pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0); + pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0); +} + /* reset bridge specific configuration registers */ void pci_bridge_reset_reg(PCIDevice *dev) { @@ -161,12 +181,28 @@ void pci_bridge_reset_reg(PCIDevice *dev) conf[PCI_SUBORDINATE_BUS] = 0; conf[PCI_SEC_LATENCY_TIMER] = 0; - conf[PCI_IO_BASE] = 0; - conf[PCI_IO_LIMIT] = 0; - pci_set_word(conf + PCI_MEMORY_BASE, 0); - pci_set_word(conf + PCI_MEMORY_LIMIT, 0); - pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0); - pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0); + /* + * the default values for base/limit registers aren't specified + * in the PCI-to-PCI-bridge spec. So we don't thouch them here. + * Each implementation can override it. + * typical implementation does + * zero base/limit registers or + * disable forwarding: pci_bridge_disable_base_limit() + * If disable forwarding is wanted, call pci_bridge_disable_base_limit() + * after this function. + */ + pci_byte_test_and_clear_mask(conf + PCI_IO_BASE, + PCI_IO_RANGE_MASK & 0xff); + pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, + PCI_IO_RANGE_MASK & 0xff); + pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE, + PCI_PREF_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, + PCI_PREF_RANGE_MASK & 0xffff); pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0); pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0); diff --git a/hw/pci_bridge.h b/hw/pci_bridge.h index f6fade0322..84411a69dc 100644 --- a/hw/pci_bridge.h +++ b/hw/pci_bridge.h @@ -39,6 +39,7 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type); void pci_bridge_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len); +void pci_bridge_disable_base_limit(PCIDevice *dev); void pci_bridge_reset_reg(PCIDevice *dev); void pci_bridge_reset(DeviceState *qdev); -- GitLab