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由 Peter Maydell 提交于
The GIC architecture specification for v1 and v2 GICs (as found on the Cortex-A9 and newer) states that the GICC_PMR reset value is zero; this differs from the 0xf0 reset value used on 11MPCore. The NVIC is different again in not having a CPU interface; since we share the GIC code we must force the priority mask field to allow through all interrupts. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@samsung.com>
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