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    Sparc32: improve interrupt handling · 462eda24
    Blue Swirl 提交于
    Level 15 interrupts are broadcast to all CPUs, each CPU can clear the
    interrupt using the local Clear Pending register.
    
    Update intbit_to_level table.
    
    Don't try to raise level 0 interrupts.
    
    Calculate pending interrupts based on the separate inputs from master
    register. Setting or resetting the pending level isn't correct because of
    overlap of levels.
    
    Level 14 is always used for CPU timer interrupts, remove the property.
    Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
    462eda24
sun4m.c 52.1 KB