armv7m.c 7.1 KB
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/*
 * ARMV7M System emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
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 * This code is licensed under the GPL.
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 */

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#include "sysbus.h"
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#include "arm-misc.h"
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#include "loader.h"
#include "elf.h"
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/* Bitbanded IO.  Each word corresponds to a single bit.  */

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/* Get the byte address of the real memory for a bitband access.  */
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static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
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{
    uint32_t res;

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    res = *(uint32_t *)opaque;
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    res |= (addr & 0x1ffffff) >> 5;
    return res;

}

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static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
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{
    uint8_t v;
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    cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
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    return (v & (1 << ((offset >> 2) & 7))) != 0;
}

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static void bitband_writeb(void *opaque, target_phys_addr_t offset,
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                           uint32_t value)
{
    uint32_t addr;
    uint8_t mask;
    uint8_t v;
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    addr = bitband_addr(opaque, offset);
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    mask = (1 << ((offset >> 2) & 7));
    cpu_physical_memory_read(addr, &v, 1);
    if (value & 1)
        v |= mask;
    else
        v &= ~mask;
    cpu_physical_memory_write(addr, &v, 1);
}

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static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
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{
    uint32_t addr;
    uint16_t mask;
    uint16_t v;
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    addr = bitband_addr(opaque, offset) & ~1;
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    mask = (1 << ((offset >> 2) & 15));
    mask = tswap16(mask);
    cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
    return (v & mask) != 0;
}

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static void bitband_writew(void *opaque, target_phys_addr_t offset,
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                           uint32_t value)
{
    uint32_t addr;
    uint16_t mask;
    uint16_t v;
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    addr = bitband_addr(opaque, offset) & ~1;
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    mask = (1 << ((offset >> 2) & 15));
    mask = tswap16(mask);
    cpu_physical_memory_read(addr, (uint8_t *)&v, 2);
    if (value & 1)
        v |= mask;
    else
        v &= ~mask;
    cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
}

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static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
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{
    uint32_t addr;
    uint32_t mask;
    uint32_t v;
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    addr = bitband_addr(opaque, offset) & ~3;
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    mask = (1 << ((offset >> 2) & 31));
    mask = tswap32(mask);
    cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
    return (v & mask) != 0;
}

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static void bitband_writel(void *opaque, target_phys_addr_t offset,
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                           uint32_t value)
{
    uint32_t addr;
    uint32_t mask;
    uint32_t v;
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    addr = bitband_addr(opaque, offset) & ~3;
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    mask = (1 << ((offset >> 2) & 31));
    mask = tswap32(mask);
    cpu_physical_memory_read(addr, (uint8_t *)&v, 4);
    if (value & 1)
        v |= mask;
    else
        v &= ~mask;
    cpu_physical_memory_write(addr, (uint8_t *)&v, 4);
}

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static const MemoryRegionOps bitband_ops = {
    .old_mmio = {
        .read = { bitband_readb, bitband_readw, bitband_readl, },
        .write = { bitband_writeb, bitband_writew, bitband_writel, },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
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};

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typedef struct {
    SysBusDevice busdev;
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    MemoryRegion iomem;
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    uint32_t base;
} BitBandState;

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static int bitband_init(SysBusDevice *dev)
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{
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    BitBandState *s = FROM_SYSBUS(BitBandState, dev);
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    memory_region_init_io(&s->iomem, &bitband_ops, &s->base, "bitband",
                          0x02000000);
    sysbus_init_mmio_region(dev, &s->iomem);
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    return 0;
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}

static void armv7m_bitband_init(void)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "ARM,bitband-memory");
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    qdev_prop_set_uint32(dev, "base", 0x20000000);
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    qdev_init_nofail(dev);
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    sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x22000000);

    dev = qdev_create(NULL, "ARM,bitband-memory");
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    qdev_prop_set_uint32(dev, "base", 0x40000000);
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    qdev_init_nofail(dev);
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    sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0x42000000);
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}

/* Board init.  */
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static void armv7m_reset(void *opaque)
{
    cpu_reset((CPUState *)opaque);
}

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/* Init CPU and memory for a v7-M based board.
   flash_size and sram_size are in kb.
   Returns the NVIC array.  */

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qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
                      int flash_size, int sram_size,
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                      const char *kernel_filename, const char *cpu_model)
{
    CPUState *env;
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    DeviceState *nvic;
    /* FIXME: make this local state.  */
    static qemu_irq pic[64];
    qemu_irq *cpu_pic;
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    int image_size;
    uint64_t entry;
    uint64_t lowaddr;
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    int i;
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    int big_endian;
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    MemoryRegion *sram = g_new(MemoryRegion, 1);
    MemoryRegion *flash = g_new(MemoryRegion, 1);
    MemoryRegion *hack = g_new(MemoryRegion, 1);
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    flash_size *= 1024;
    sram_size *= 1024;

    if (!cpu_model)
	cpu_model = "cortex-m3";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }

#if 0
    /* > 32Mb SRAM gets complicated because it overlaps the bitband area.
       We don't have proper commandline options, so allocate half of memory
       as SRAM, up to a maximum of 32Mb, and the rest as code.  */
    if (ram_size > (512 + 32) * 1024 * 1024)
        ram_size = (512 + 32) * 1024 * 1024;
    sram_size = (ram_size / 2) & TARGET_PAGE_MASK;
    if (sram_size > 32 * 1024 * 1024)
        sram_size = 32 * 1024 * 1024;
    code_size = ram_size - sram_size;
#endif

    /* Flash programming is done via the SCU, so pretend it is ROM.  */
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    memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size);
    memory_region_set_readonly(flash, true);
    memory_region_add_subregion(address_space_mem, 0, flash);
    memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size);
    memory_region_add_subregion(address_space_mem, 0x20000000, sram);
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    armv7m_bitband_init();

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    nvic = qdev_create(NULL, "armv7m_nvic");
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    env->nvic = nvic;
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    qdev_init_nofail(nvic);
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    cpu_pic = arm_pic_init_cpu(env);
    sysbus_connect_irq(sysbus_from_qdev(nvic), 0, cpu_pic[ARM_PIC_CPU_IRQ]);
    for (i = 0; i < 64; i++) {
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        pic[i] = qdev_get_gpio_in(nvic, i);
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    }
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#ifdef TARGET_WORDS_BIGENDIAN
    big_endian = 1;
#else
    big_endian = 0;
#endif

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    image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr,
                          NULL, big_endian, ELF_MACHINE, 1);
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    if (image_size < 0) {
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        image_size = load_image_targphys(kernel_filename, 0, flash_size);
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	lowaddr = 0;
    }
    if (image_size < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
                kernel_filename);
        exit(1);
    }

    /* Hack to map an additional page of ram at the top of the address
       space.  This stops qemu complaining about executing code outside RAM
       when returning from an exception.  */
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    memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000);
    memory_region_add_subregion(address_space_mem, 0xfffff000, hack);
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    qemu_register_reset(armv7m_reset, env);
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    return pic;
}
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static SysBusDeviceInfo bitband_info = {
    .init = bitband_init,
    .qdev.name  = "ARM,bitband-memory",
    .qdev.size  = sizeof(BitBandState),
    .qdev.props = (Property[]) {
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        DEFINE_PROP_UINT32("base", BitBandState, base, 0),
        DEFINE_PROP_END_OF_LIST(),
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    }
};

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static void armv7m_register_devices(void)
{
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    sysbus_register_withprop(&bitband_info);
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}

device_init(armv7m_register_devices)