From e7cb9c4e230c3c77e35e72334c261b5b0a2211c6 Mon Sep 17 00:00:00 2001
From: Shaohe Feng <shaohe.feng@intel.com>
Date: Sun, 17 Dec 2017 18:02:44 -0500
Subject: [PATCH] cpu: Add support for al57 Intel features

We can start qemu with a "cpu,+la57" to set 57-bit vitrual address
space. So VM can be aware that it need to enable 5-level paging.

Corresponding QEMU commits:
        al57 6c7c3c21f95dd9af8a0691c0dd29b07247984122
---
 src/cpu/cpu_map.xml                                  | 3 +++
 tests/domaincapsschemadata/qemu_2.9.0-tcg.x86_64.xml | 1 +
 2 files changed, 4 insertions(+)

diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml
index 85c728227f..00a43b172c 100644
--- a/src/cpu/cpu_map.xml
+++ b/src/cpu/cpu_map.xml
@@ -285,6 +285,9 @@
     <feature name='ospke'>
       <cpuid eax_in='0x07' ecx_in='0x00' ecx='0x00000010'/>
     </feature>
+    <feature name='la57'>
+      <cpuid eax_in='0x07' ecx_in='0x00' ecx='0x00010000'/>
+    </feature>
 
     <feature name='avx512-4vnniw'>
       <cpuid eax_in='0x07' ecx_in='0x00' edx='0x00000004'/>
diff --git a/tests/domaincapsschemadata/qemu_2.9.0-tcg.x86_64.xml b/tests/domaincapsschemadata/qemu_2.9.0-tcg.x86_64.xml
index 7ff998907d..6c2bbac190 100644
--- a/tests/domaincapsschemadata/qemu_2.9.0-tcg.x86_64.xml
+++ b/tests/domaincapsschemadata/qemu_2.9.0-tcg.x86_64.xml
@@ -43,6 +43,7 @@
       <feature policy='require' name='clwb'/>
       <feature policy='require' name='pku'/>
       <feature policy='require' name='ospke'/>
+      <feature policy='require' name='la57'/>
       <feature policy='require' name='xsaveopt'/>
       <feature policy='require' name='xgetbv1'/>
       <feature policy='require' name='mmxext'/>
-- 
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