* AHCI SATA Controller

SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.

It is possible, but not required, to represent each port as a sub-node.
It allows to enable each port independently when dealing with multiple
PHYs.

Required properties:
- compatible        : compatible string, one of:
  - "allwinner,sun4i-a10-ahci"
  - "hisilicon,hisi-ahci"
  - "cavium,octeon-7130-ahci"
  - "ibm,476gtr-ahci"
  - "marvell,armada-380-ahci"
  - "snps,dwc-ahci"
  - "snps,exynos5440-ahci"
  - "snps,spear-ahci"
  - "generic-ahci"
- interrupts        : <interrupt mapping for SATA IRQ>
- reg               : <registers mapping>

Please note that when using "generic-ahci" you must also specify a SoC specific
compatible:
	compatible = "manufacturer,soc-model-ahci", "generic-ahci";

Optional properties:
- dma-coherent      : Present if dma operations are coherent
- clocks            : a list of phandle + clock specifier pairs
- target-supply     : regulator for SATA target power
- phys              : reference to the SATA PHY node
- phy-names         : must be "sata-phy"

Required properties when using sub-nodes:
- #address-cells    : number of cells to encode an address
- #size-cells       : number of cells representing the size of an address


Sub-nodes required properties:
- reg		    : the port number
And at least one of the following properties:
- phys		    : reference to the SATA PHY node
- target-supply    : regulator for SATA target power

Examples:
        sata@ffe08000 {
		compatible = "snps,spear-ahci";
		reg = <0xffe08000 0x1000>;
		interrupts = <115>;
        };

	ahci: sata@01c18000 {
		compatible = "allwinner,sun4i-a10-ahci";
		reg = <0x01c18000 0x1000>;
		interrupts = <56>;
		clocks = <&pll6 0>, <&ahb_gates 25>;
		target-supply = <&reg_ahci_5v>;
	};

With sub-nodes:
	sata@f7e90000 {
		compatible = "marvell,berlin2q-achi", "generic-ahci";
		reg = <0xe90000 0x1000>;
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&chip CLKID_SATA>;
		#address-cells = <1>;
		#size-cells = <0>;

		sata0: sata-port@0 {
			reg = <0>;
			phys = <&sata_phy 0>;
			target-supply = <&reg_sata0>;
		};

		sata1: sata-port@1 {
			reg = <1>;
			phys = <&sata_phy 1>;
			target-supply = <&reg_sata1>;;
		};
	};