Device Tree Clock bindings for arch-sunxi

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be one of the following:
	"allwinner,sun4i-osc-clk" - for a gatable oscillator
	"allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
	"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
	"allwinner,sun4i-pll5-clk" - for the PLL5 clock
	"allwinner,sun4i-pll6-clk" - for the PLL6 clock
	"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
	"allwinner,sun4i-axi-clk" - for the AXI clock
	"allwinner,sun4i-axi-gates-clk" - for the AXI gates
	"allwinner,sun4i-ahb-clk" - for the AHB clock
	"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
	"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
	"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
	"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
	"allwinner,sun4i-apb0-clk" - for the APB0 clock
	"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
	"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
	"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
	"allwinner,sun4i-apb1-clk" - for the APB1 clock
	"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
	"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
	"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
	"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
	"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
	"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
	"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
	"allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
	"allwinner,sun7i-a20-out-clk" - for the external output clocks

Required properties for all clocks:
- reg : shall be the control register address for the clock.
- clocks : shall be the input parent clock(s) phandle for the clock. For
	multiplexed clocks, the list order must match the hardware
	programming order.
- #clock-cells : from common clock binding; shall be set to 0 except for
	"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
	"allwinner,sun4i-pll6-clk" where it shall be set to 1
- clock-output-names : shall be the corresponding names of the outputs.
	If the clock module only has one output, the name shall be the
	module name.

Clock consumers should specify the desired clocks they use with a
"clocks" phandle cell. Consumers that are using a gated clock should
provide an additional ID in their clock property. This ID is the
offset of the bit controlling this particular gate in the register.

For example:

osc24M: clk@01c20050 {
	#clock-cells = <0>;
	compatible = "allwinner,sun4i-osc-clk";
	reg = <0x01c20050 0x4>;
	clocks = <&osc24M_fixed>;
	clock-output-names = "osc24M";
};

pll1: clk@01c20000 {
	#clock-cells = <0>;
	compatible = "allwinner,sun4i-pll1-clk";
	reg = <0x01c20000 0x4>;
	clocks = <&osc24M>;
	clock-output-names = "pll1";
};

pll5: clk@01c20020 {
	#clock-cells = <1>;
	compatible = "allwinner,sun4i-pll5-clk";
	reg = <0x01c20020 0x4>;
	clocks = <&osc24M>;
	clock-output-names = "pll5_ddr", "pll5_other";
};

cpu: cpu@01c20054 {
	#clock-cells = <0>;
	compatible = "allwinner,sun4i-cpu-clk";
	reg = <0x01c20054 0x4>;
	clocks = <&osc32k>, <&osc24M>, <&pll1>;
	clock-output-names = "cpu";
};

mmc0_clk: clk@01c20088 {
	#clock-cells = <0>;
	compatible = "allwinner,sun4i-mod0-clk";
	reg = <0x01c20088 0x4>;
	clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
	clock-output-names = "mmc0";
};