// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2020 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

lsio_subsys: bus@5d000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;

	lsio_gpio0: gpio@5d080000 {
		reg = <0x5d080000 0x10000>;
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		power-domains = <&pd IMX_SC_R_GPIO_0>;
	};

	lsio_gpio1: gpio@5d090000 {
		reg = <0x5d090000 0x10000>;
		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		power-domains = <&pd IMX_SC_R_GPIO_1>;
	};

	lsio_gpio2: gpio@5d0a0000 {
		reg = <0x5d0a0000 0x10000>;
		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		power-domains = <&pd IMX_SC_R_GPIO_2>;
	};

	lsio_gpio3: gpio@5d0b0000 {
		reg = <0x5d0b0000 0x10000>;
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		power-domains = <&pd IMX_SC_R_GPIO_3>;
	};

	lsio_gpio4: gpio@5d0c0000 {
		reg = <0x5d0c0000 0x10000>;
		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		power-domains = <&pd IMX_SC_R_GPIO_4>;
	};

	lsio_gpio5: gpio@5d0d0000 {
		reg = <0x5d0d0000 0x10000>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		power-domains = <&pd IMX_SC_R_GPIO_5>;
	};

	lsio_gpio6: gpio@5d0e0000 {
		reg = <0x5d0e0000 0x10000>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		power-domains = <&pd IMX_SC_R_GPIO_6>;
	};

	lsio_gpio7: gpio@5d0f0000 {
		reg = <0x5d0f0000 0x10000>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		power-domains = <&pd IMX_SC_R_GPIO_7>;
	};

	lsio_mu0: mailbox@5d1b0000 {
		reg = <0x5d1b0000 0x10000>;
		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <2>;
		status = "disabled";
	};

	lsio_mu1: mailbox@5d1c0000 {
		reg = <0x5d1c0000 0x10000>;
		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <2>;
	};

	lsio_mu2: mailbox@5d1d0000 {
		reg = <0x5d1d0000 0x10000>;
		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <2>;
		status = "disabled";
	};

	lsio_mu3: mailbox@5d1e0000 {
		reg = <0x5d1e0000 0x10000>;
		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <2>;
		status = "disabled";
	};

	lsio_mu4: mailbox@5d1f0000 {
		reg = <0x5d1f0000 0x10000>;
		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <2>;
		status = "disabled";
	};

	lsio_mu13: mailbox@5d280000 {
		reg = <0x5d280000 0x10000>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <2>;
		power-domains = <&pd IMX_SC_R_MU_13A>;
	};

	lsio_lpcg: clock-controller@5d400000 {
		reg = <0x5d400000 0x400000>;
		#clock-cells = <1>;
	};
};