// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2020 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

adma_subsys: bus@59000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x59000000 0x0 0x59000000 0x2000000>;

	adma_lpcg: clock-controller@59000000 {
		reg = <0x59000000 0x2000000>;
		#clock-cells = <1>;
	};

	adma_dsp: dsp@596e8000 {
		compatible = "fsl,imx8qxp-dsp";
		reg = <0x596e8000 0x88000>;
		clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
			<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
			<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
		clock-names = "ipg", "ocram", "core";
		power-domains = <&pd IMX_SC_R_MU_13A>,
			<&pd IMX_SC_R_MU_13B>,
			<&pd IMX_SC_R_DSP>,
			<&pd IMX_SC_R_DSP_RAM>;
		mbox-names = "txdb0", "txdb1",
			"rxdb0", "rxdb1";
		mboxes = <&lsio_mu13 2 0>,
			<&lsio_mu13 2 1>,
			<&lsio_mu13 3 0>,
			<&lsio_mu13 3 1>;
		memory-region = <&dsp_reserved>;
		status = "disabled";
	};

	adma_lpuart0: serial@5a060000 {
		reg = <0x5a060000 0x1000>;
		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
			 <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
		clock-names = "ipg", "baud";
		power-domains = <&pd IMX_SC_R_UART_0>;
		status = "disabled";
	};

	adma_lpuart1: serial@5a070000 {
		reg = <0x5a070000 0x1000>;
		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
			 <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
		clock-names = "ipg", "baud";
		power-domains = <&pd IMX_SC_R_UART_1>;
		status = "disabled";
	};

	adma_lpuart2: serial@5a080000 {
		reg = <0x5a080000 0x1000>;
		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
			 <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
		clock-names = "ipg", "baud";
		power-domains = <&pd IMX_SC_R_UART_2>;
		status = "disabled";
	};

	adma_lpuart3: serial@5a090000 {
		reg = <0x5a090000 0x1000>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
			 <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
		clock-names = "ipg", "baud";
		power-domains = <&pd IMX_SC_R_UART_3>;
		status = "disabled";
	};

	adma_i2c0: i2c@5a800000 {
		reg = <0x5a800000 0x4000>;
		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
		clock-names = "per";
		assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_0>;
		status = "disabled";
	};

	adma_i2c1: i2c@5a810000 {
		reg = <0x5a810000 0x4000>;
		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
		clock-names = "per";
		assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_1>;
		status = "disabled";
	};

	adma_i2c2: i2c@5a820000 {
		reg = <0x5a820000 0x4000>;
		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
		clock-names = "per";
		assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_2>;
		status = "disabled";
	};

	adma_i2c3: i2c@5a830000 {
		reg = <0x5a830000 0x4000>;
		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
		clock-names = "per";
		assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
		assigned-clock-rates = <24000000>;
		power-domains = <&pd IMX_SC_R_I2C_3>;
		status = "disabled";
	};
};