This commit adds support for the HDMI output on the Tegra20 SoC. Only
one such output is available, but it can be driven by either of the two
display controllers.

A lot of work on this patch has been contributed by NVIDIA's Mark Zhang
<markz@nvidia.com> and many other people at NVIDIA were very helpful in
getting the HDMI support and surrounding infrastructure to work.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NMark Zhang <markz@nvidia.com>
Reviewed-by: NMark Zhang <markz@nvidia.com>
Tested-by: NMark Zhang <markz@nvidia.com>
Tested-and-acked-by: NAlexandre Courbot <acourbot@nvidia.com>
Acked-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Tested-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

This commit adds a KMS driver for the Tegra20 SoC. This includes basic
support for host1x and the two display controllers found on the Tegra20
SoC. Each display controller can drive a separate RGB/LVDS output.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NMark Zhang <markz@nvidia.com>
Reviewed-by: NMark Zhang <markz@nvidia.com>
Tested-by: NMark Zhang <markz@nvidia.com>
Tested-and-acked-by: NAlexandre Courbot <acourbot@nvidia.com>
Acked-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Tested-by: NTerje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Fixes the following sparse warnings:
drivers/gpu/drm/udl/udl_connector.c:80:20: warning:
symbol 'udl_best_single_encoder' was not declared. Should it be static?
drivers/gpu/drm/udl/udl_connector.c:93:5: warning:
symbol 'udl_connector_set_property' was not declared. Should it be static?
drivers/gpu/drm/udl/udl_connector.c:106:35: warning:
symbol 'udl_connector_helper_funcs' was not declared. Should it be static?
drivers/gpu/drm/udl/udl_connector.c:112:28: warning:
symbol 'udl_connector_funcs' was not declared. Should it be static?
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

kfree on a null argument is a no-op.
Silences the following smatch warning:
drivers/gpu/drm/drm_stub.c:496 drm_put_dev() info:
redundant null check on dev->devname calling kfree()
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NDave Airlie <airlied@redhat.com>

kcalloc returns NULL on failure. Hence check for the return value
and exit on error to avoid NULL pointer dereference.

Fixes the following smatch errors:
drivers/gpu/drm/drm_fb_helper.c:1271 drm_setup_crtcs() error:
potential null dereference 'modes'.  (kcalloc returns null)
drivers/gpu/drm/drm_fb_helper.c:1272 drm_setup_crtcs() error:
potential null dereference 'crtcs'.  (kcalloc returns null)
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NDave Airlie <airlied@redhat.com>

drm_property_create_blob() could return NULL in which case NULL pointer
dereference error (on connector->edid_blob_ptr) is possible. Return if
connector->edid_blob_ptr is NULL.

Fixes the following smatch error:
drivers/gpu/drm/drm_crtc.c:3186 drm_mode_connector_update_edid_property()
error: potential null dereference 'connector->edid_blob_ptr'.
(drm_property_create_blob returns null)
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NDave Airlie <airlied@redhat.com>

kfree() on a NULL input is a no-op. Hence remove the check.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

x and y parameters are offsets, not width/height
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: NDave Airlie <airlied@redhat.com>

This patch adds support for getting CEA Video ID Code for a given
display mode after matching with edid_cea_modes list. Its index in
the list added with one, gives the desired code.

This exported function will be used by hdmi drivers for composing
AVI info frame data.
Signed-off-by: NStephane Marchesin <marcheu@chromium.org>
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Remove unnecessary braces to silence the following type of
checkpatch warnings:
WARNING: braces {} are not necessary for single statement blocks
WARNING: braces {} are not necessary for any arm of this statement
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Converted printks to pr_* and dev_* to silence checkpatch warnings.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Fixes the following checkpatch errors:
ERROR: trailing statements should be on next line
98: FILE: gpu/drm/drm_fb_helper.c:98:
	case DRM_FORCE_OFF: s = "OFF"; break;
ERROR: trailing statements should be on next line
99: FILE: gpu/drm/drm_fb_helper.c:99:
	case DRM_FORCE_ON_DIGITAL: s = "ON - dig"; break;
ERROR: trailing statements should be on next line
101: FILE: gpu/drm/drm_fb_helper.c:101:
	case DRM_FORCE_ON: s = "ON"; break;
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NDave Airlie <airlied@redhat.com>

We link every DRM "file_priv" to a "drm_master" structure. Currently, the
drmSetMaster() call returns 0 when there is _any_ active master associated
with the "drm_master" structure of the calling "file_priv". This means,
that after drmSetMaster() we are not guaranteed to be DRM-Master and might
not be able to perform mode-setting.

A way to reproduce this is by starting weston with the DRM backend from
within an X-console (eg., xterm). Because the xserver's "drm_master" is
currently active, weston is assigned to the same master but is inactive
because its VT is inactive and the xserver is still active. But when
"fake-activating" weston, it calls drmSetMaster(). With current behavior
this returns "0/success" and weston thinks that it is DRM-Master, even
though it is not (as the xserver is still DRM-Master).
Expected behavior would be drmSetMaster() to return -EINVAL, because the
xserver is still DRM-Master. This patch changes exactly that.

The only way this bogus behavior would be useful is for clients to check
whether their associated "drm_master" is currently the active DRM-Master.
But this logic fails if no DRM-Master is currently active at all. Because
then the client itself would become DRM-Master (if it is root) and this
makes this whole thing useles.

Also note that the second "if-condition":
  file_priv->minor->master != file_priv->master
is always true and can be skipped.
Signed-off-by: NDavid Herrmann <dh.herrmann@googlemail.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

By always setting up the HWS register for both physical and virtual
address variations during render ring we can reduce the number of
different special cases that get set up at varying different times
during module load.

Fixes regression from

commit c630119f
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Wed Oct 17 11:32:57 2012 +0200

    drm/i915: don't save/restore HWS_PGA reg for kms
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

...rather than kilo-PTE.
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
[danvet: Apply s/Usabel/usable/ bikeshed suggested by Ben Widawsky.]
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

This fixes a regression for SDVO from

commit fbfcc4f3
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Mon Oct 22 16:12:18 2012 +0300

    drm/i915/sdvo: restore i2c adapter config on intel_sdvo_init() failures

As SDVOB and SDVOC are multiplexed on the same pin, if a chipset does
not have the second SDVO encoder, it will then remove the force-bit
setting on the common i2c adapter during teardown. All subsequent
attempts of trying to use GMBUS with SDVOB then fail.
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
[danvet: fixup inversion in the debug printout, noticed by Jani
Nikulai.]
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Whoops. This was fixed previously, but not sure how it got lost. It's
not needed for -fixes or stable because at the moment
drm_i915_file_private is way bigger than i915_hw_context (by 120 bytes
on my 64b build).
Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

After the rework, intel_set_mode() became a little better behaved in
restoring the current mode if we failed to apply the requested modeline.
However, the failure path for load-detect would clobber the existing
state, leading to an oops during BIOS takeover on older machines.
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

With the stricter checks introduced in
commit ac911edae5960d7dccd9883f5fa5d25b591520de
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Wed Oct 31 17:50:19 2012 +0200

    drm/i915: Check the framebuffer offset

(and friends), it became especially prudent to make sure that the
additional fields inside the mode were cleared before attempting to
create a framebuffer. In particular, the fb created for load detection
failed to do so and hence failed.
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

The specs for gen2 say that the watermark values "should always be set
assuming a 32bpp display mode, even though the display mode may be 15 or
16 bpp."
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Reported-by: NFengguang Wu <fengguang.wu@intel.com>
Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Fixes a WARN_ON in igt/tests/debugfs_reader

CC: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

It's pretty much all consolidated now that we've killed AGP. We can move
the one outlier, and defines too.

(Kill some unused defines in the process)
Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

This allows us to map the PTEs WC. I've not done thorough testing or
performance measurements with this patch, but it should be decent.

This is based on a patch from Jesse with the original commit message
> I've only lightly tested this so far, but the corruption seems to be
> gone if I write the GFX_FLSH_CNTL reg after binding an object.  This
> register should control the TLB for the system agent, which is what CPU
> mapped objects will go through.

It has been updated for the new AGP-less code by me, and included with
it is feedback from the original patch.

v2: Updated to reflect paranoia on pte updates/register posting reads.
Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
Reviewed-by [v1]: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

v2: Accidently removed an ILK case in i9xx_setup (Nicely found by Chris)

CC: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by [v1] : Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

This bug existed in the old code, but was easier to fix here in the
rework. Unfortunately gen7 doesn't have a nice way to figure out the
size and we must use a lookup table.

As Jesse pointed out, there is some confusion in the docs about these
definitions. We're picking the one which seems more accurate, but we
really aren't certain.
Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

As a quick hack we make the old intel_gtt structure mutable so we can
fool a bunch of the existing code which depends on elements in that data
structure. We can/should try to remove this in a subsequent patch.

This should preserve the old gtt init behavior which upon writing these
patches seems incorrect. The next patch will fix these things.

The one exception is VLV which doesn't have the preserved flush control
write behavior. Since we want to do that for all GEN6+ stuff, we'll
handle that in a later patch. Mainstream VLV support doesn't actually
exist yet anyway.

v2: Update the comment to remove the "voodoo"
Check that the last pte written matches what we readback

v3: actually kill cache_level_to_agp_type since most of the flags will
disappear in an upcoming patch

v4: v3 was actually not what we wanted (Daniel)
Make the ggtt bind assertions better and stricter (Chris)
Fix some uncaught errors at gtt init (Chris)
Some other random stuff that Chris wanted

v5: check for i==0 in gen6_ggtt_bind_object to shut up gcc (Ben)
Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
Reviewed-by [v4]: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Make the cache_level -> agp_flags conversion for pre-gen6 a
tad more robust by mapping everything != CACHE_NONE to the cached agp
flag - we have a 1:1 uncached mapping, but different modes of
cacheable (at least on later generations). Suggested by Chris Wilson.]
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

This has been introduced in "drm/i915: TLB invalidation with
MI_FLUSH_DW requires a post-sync op".
Reported-by: NFengguang Wu <fengguang.wu@intel.com>
Reported-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

The BIOS shouldn't be touching this memory across suspend/resume, so
just leave it alone.  This saves us ~6ms on resume on my T420 (retested
with write combined PTEs).

v2: change gtt restore default on pre-gen4 (Chris)
    move needs_gtt_restore flag into dev_priv
v3: make sure we restore GTT on resume from hibernate (Daniel)
    use opregion support as the cutoff for restore from resume (Chris)
v4: use a better check for opregion (Chris)
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Kill the needs_gtt_restore indirection and check directly for
OpRegion. Also explain in a comment what's going on.]
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

This allows the power related code to run independently of the rest of
the pipeline, extending the resume and init time improvements into
userspace, which would otherwise have been blocked on the struct mutex
if we were doing PCU communication.

v2: Also convert the locking for the rps sysfs interface.
Suggested-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v1)
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Communicating via the mailbox registers with the PCU can take quite
awhile.  And updating the ring frequency or enabling turbo is not
something that needs to happen synchronously, so take it out of our init
and resume paths to speed things up (~200ms on my T420).

v2: add comment about why we use a work queue (Daniel)
    make sure work queue is idle on suspend (Daniel)
    use a delayed work queue since there's no hurry (Daniel)
v3: make cleanup symmetric and just call cancel work directly (Daniel)
v4: schedule the work using round_jiffies_up to batch work better (Chris)
v5: fix the right schedule_delayed_work call (Chris)

References: https://bugs.freedesktop.org/show_bug.cgi?id=54089Signed-of-by: NJesse Barnes <jbarnes@virtuougseek.org>
[danvet: bikeshed the placement of the new delayed work, move it to
all the other gen6 power mgmt stuff.]
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

The console lock can be contended, so rather than prevent other drivers
after us from being held up, queue the console suspend into the global
work queue that can happen anytime.  I've measured this to take around
200ms on my T420.  Combined with the ring freq/turbo change, we should
save almost 1/2 a second on resume.

v2: use console_trylock() to try to resume the console immediately (Chris)
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
[danvet: move dev_priv->console_resume_work next to the fbdev
pointer.]
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Pretty astonishing how far apart these two members landed ... Especially since
I've already removed almost 200 lines in between.
Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Also, move dev_priv->counter there, it's only used in i915_dma.c

And also move the dri1 dungeon at the end of dev_priv where no one
cares about it.
Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

And give the structs slightly more generic names. I've decided to keep
the short rps/ips prefix, since that's just easier and less churn.
Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

dev_priv has grown way too big, and grouping memebers into substructs
and moving them out of line helps re-gain some overview.

Unfortunatley I couldn't just call the substruct save and drop the prefix, since
that will make most member names clash with registers #defines. Changes in
i915_drv.h done by hand, everything else changed with
s/\<save\([A-Z]*\)/regfile.save\1/ in vim.
Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

So we can write them properly.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: NAntti Koskipää <antti.koskipaa@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

"If ENABLED, PIPE_CONTROL command will flush the in flight data  written
out by render engine to Global Observation point on flush done. Also
Requires stall bit ([20] of DW1) set."

So set the stall bit to ensure proper invalidation.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: NAntti Koskipää <antti.koskipaa@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>