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  1. 13 6月, 2016 1 次提交
  3. 08 6月, 2016 1 次提交
  5. 01 6月, 2016 1 次提交
  7. 11 5月, 2016 2 次提交
  9. 05 5月, 2016 1 次提交
  11. 19 4月, 2016 1 次提交
  13. 01 4月, 2016 1 次提交
  15. 07 3月, 2016 1 次提交
  17. 17 2月, 2016 1 次提交
  19. 11 2月, 2016 8 次提交
  21. 26 1月, 2016 2 次提交
    • J
      net: fec: use CONFIG_ARM instead of CONFIG_ARCH_MXC/SOC_IMX28 · 05f3b50e
      由 Johannes Berg 提交于 
      As Arnd Bergmann points out, using CONFIG_ARCH_MXC and/or SOC_IMX28
is wrong if some other ARM platform uses this device - the operation
of the driver would depend on an unrelated ARM platform that might
or might not be set for multi-platform kernels.

Prior to my previous patch, any other platforms using it would have
been broken already due to having the cbd_datlen/cbd_sc fields in
the wrong order, but byte ordering correctly, so no such platforms
can exist and work today.

In any case, it seems likely that only Freescale SoCs use this part,
and those are little-endian on ARM, so CONFIG_ARM is safe for them.
Signed-off-by: NJohannes Berg <johannes@sipsolutions.net>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      05f3b50e
    • J
      net: fec: make driver endian-safe · 5cfa3039
      由 Johannes Berg 提交于 
      The driver treats the device descriptors as CPU-endian, which appears
to be correct with the default endianness on both ARM (typically LE)
and PowerPC (typically BE) SoCs, indicating that the hardware block
is generated differently. Add endianness annotations and byteswaps as
necessary.

It's not clear that the ifdef there really is correct and shouldn't
just be #ifdef CONFIG_ARM, but I also can't test on anything but the
i.MX6 HummingBoard where this gets it working with a BE kernel.
Signed-off-by: NJohannes Berg <johannes@sipsolutions.net>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5cfa3039
  23. 08 1月, 2016 3 次提交
  25. 25 11月, 2015 1 次提交
  27. 02 11月, 2015 1 次提交
  29. 29 9月, 2015 1 次提交
  31. 10 9月, 2015 1 次提交
    • N
      net: fec: add netif status check before set mac address · 9638d19e
      由 Nimrod Andy 提交于 
      There exist one issue by below case that case system hang:
ifconfig eth0 down
ifconfig eth0 hw ether 00:10:19:19:81:19

After eth0 down, all fec clocks are gated off. In the .fec_set_mac_address()
function, it will set new MAC address to registers, which causes system hang.

So it needs to add netif status check to avoid registers access when clocks are
gated off. Until eth0 up the new MAC address are wrote into related registers.

V2:
As Lucas Stach's suggestion, add a comment in the code to explain why it needed.

CC: Lucas Stach <l.stach@pengutronix.de>
CC: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9638d19e
  33. 06 9月, 2015 1 次提交
  35. 03 9月, 2015 1 次提交
  37. 26 8月, 2015 1 次提交
    • R
      net: fec: use reinit_completion() in mdio accessor functions · aac27c7a
      由 Russell King 提交于 
      Rather than re-initialising the entire completion on every mdio access,
use reinit_completion() which only resets the completion count.  This
avoids possible reinitialisation of the contained spinlock and waitqueue
while they may be in use (eg, mid-completion.)

Such an event could occur if there's a long delay in interrupt handling
causing the mdio accessor to time out, then a second access comes in
while the interrupt handler on a different CPU has called complete().
Another scenario where this has been observed is while locking has
been missing at the phy layer, allowing concurrent attempts to access
the MDIO bus.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      aac27c7a
  39. 13 8月, 2015 1 次提交
  41. 11 8月, 2015 1 次提交
    • K
      net: fec: fix the race between xmit and bdp reclaiming path · c4bc44c6
      由 Kevin Hao 提交于 
      When we transmit a fragmented skb, we may run into a race like the
following scenario (assume txq->cur_tx is next to txq->dirty_tx):
           cpu 0                                          cpu 1
  fec_enet_txq_submit_skb
    reserve a bdp for the first fragment
    fec_enet_txq_submit_frag_skb
       update the bdp for the other fragment
       update txq->cur_tx
                                                   fec_enet_tx_queue
                                                     bdp = fec_enet_get_nextdesc(txq->dirty_tx, fep, queue_id);
                                                     This bdp is the bdp reserved for the first segment. Given
                                                     that this bdp BD_ENET_TX_READY bit is not set and txq->cur_tx
                                                     is already pointed to a bdp beyond this one. We think this is a
                                                     completed bdp and try to reclaim it.
    update the bdp for the first segment
    update txq->cur_tx

So we shouldn't update the txq->cur_tx until all the update to the
bdps used for fragments are performed. Also add the corresponding
memory barrier to guarantee that the update to the bdps, dirty_tx and
cur_tx performed in the proper order.
Signed-off-by: NKevin Hao <haokexin@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c4bc44c6
  43. 07 8月, 2015 1 次提交
  45. 27 7月, 2015 3 次提交
  47. 16 7月, 2015 1 次提交
  49. 09 7月, 2015 1 次提交
    • A
      net: fec: Ensure clocks are enabled while using mdio bus · 6c3e921b
      由 Andrew Lunn 提交于 
      When a switch is attached to the mdio bus, the mdio bus can be used
while the interface is not open. If the IPG clock is not enabled, MDIO
reads/writes will simply time out.

Add support for runtime PM to control this clock. Enable/disable this
clock using runtime PM, with open()/close() and mdio read()/write()
function triggering runtime PM operations. Since PM is optional, the
IPG clock is enabled at probe and is no longer modified by
fec_enet_clk_enable(), thus if PM is not enabled in the kernel, it is
guaranteed the clock is running when MDIO operations are performed.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Acked-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6c3e921b
  51. 29 6月, 2015 1 次提交
    • G
      net: fec: don't access RACC register when not available · 18803495
      由 Greg Ungerer 提交于 
      Not all silicon implementations of the Freescale FEC hardware module
have the RACC (Receive Accelerator Function) register, so we should not
be trying to access it on those that don't. Currently none of the ColdFire
based parts with a FEC have it.

Support for RACC was introduced by commit 4c09eed9 ("net: fec: Enable imx6
enet checksum acceleration"). A fix was introduced in commit d1391930
("net: fec: Fix build for MCF5272") that disables its use on the ColdFire
M5272 part, but it doesn't fix the general case of other ColdFire parts.

To fix we create a quirk flag, FEC_QUIRK_HAS_RACC, and check it before
working with the RACC register.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      18803495
  53. 23 6月, 2015 1 次提交
    • N
      net: fec: init MAC prior to mii bus probe · 55dd2753
      由 Nimrod Andy 提交于 
      Below case causes mii bus probe failed:
ifconfig eth0 down -> suspend/resume with Mega/fax mix off -> ifconfig eth0 up

In i.MX6SX/i.MX7D chip, Mega/fast mix off feature is supported that means most of
SOC power will be off including ENET MAC for power saving. Once ENET MAC power
off, all initialized MAC registers reset to default, so in the case, it must
init MAC prior to mii bus probe.
Signed-off-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      55dd2753