1. 08 2月, 2007 6 次提交
  2. 08 12月, 2006 2 次提交
  3. 19 10月, 2006 1 次提交
  4. 04 10月, 2006 8 次提交
    • E
      [PATCH] msi: refactor and move the msi irq_chip into the arch code · 3b7d1921
      Eric W. Biederman 提交于
      It turns out msi_ops was simply not enough to abstract the architecture
      specific details of msi.  So I have moved the resposibility of constructing
      the struct irq_chip to the architectures, and have two architecture specific
      functions arch_setup_msi_irq, and arch_teardown_msi_irq.
      
      For simple architectures those functions can do all of the work.  For
      architectures with platform dependencies they can call into the appropriate
      platform code.
      
      With this msi.c is finally free of assuming you have an apic, and this
      actually takes less code.
      
      The helpers for the architecture specific code are declared in the linux/msi.h
      to keep them separate from the msi functions used by drivers in linux/pci.h
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Greg KH <greg@kroah.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      3b7d1921
    • E
      [PATCH] msi: only use a single irq_chip for msi interrupts · 277bc33b
      Eric W. Biederman 提交于
      The logic works like this.
      
      Since we no longer track the state logic by hand in msi.c startup and shutdown
      are no longer needed.
      
      By updating msi_set_mask_bit to work on msi devices that do not implement a
      mask bit we can always call the mask/unmask functions.
      
      What we really have are mask and unmask so we use them to implement the .mask
      and .unmask functions instead of .enable and .disable.
      
      By switching to the handle_edge_irq handler we only need an ack function that
      moves the irq if necessary.  Which removes the old end and ack functions and
      their peculiar logic of sometimes disabling an irq.
      
      This removes the reliance on pre genirq irq handling methods.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Greg KH <greg@kroah.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      277bc33b
    • E
      [PATCH] msi: simplify msi sanity checks by adding with generic irq code · 1f80025e
      Eric W. Biederman 提交于
      Currently msi.c is doing sanity checks that make certain before an irq is
      destroyed it has no more users.
      
      By adding irq_has_action I can perform the test is a generic way, instead of
      relying on a msi specific data structure.
      
      By performing the core check in dynamic_irq_cleanup I ensure every user of
      dynamic irqs has a test present and we don't free resources that are in use.
      
      In msi.c this allows me to kill the attrib.state member of msi_desc and all of
      the assciated code to maintain it.
      
      To keep from freeing data structures when irq cleanup code is called to soon
      changing dyanamic_irq_cleanup is insufficient because there are msi specific
      data structures that are also not safe to free.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Greg KH <greg@kroah.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      1f80025e
    • E
      [PATCH] genirq: msi: make the msi code irq based and not vector based · 1ce03373
      Eric W. Biederman 提交于
      The msi currently allocates irqs backwards.  First it allocates a platform
      dependent routing value for an interrupt the ``vector'' and then it figures
      out from the vector which irq you are on.
      
      For ia64 this is fine.  For x86 and x86_64 this is complete nonsense and makes
      an enourmous mess of the irq handling code and prevents some pretty
      significant cleanups in the code for handling large numbers of irqs.
      
      This patch refactors msi.c to work in terms of irqs and create_irq/destroy_irq
      for dynamically managing irqs.
      
      Hopefully this is finally a version of msi.c that is useful on more than just
      x86 derivatives.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      1ce03373
    • E
      [PATCH] genirq: msi: simplify the msi irq limit policy · 92db6d10
      Eric W. Biederman 提交于
      Currently we attempt to predict how many irqs we will be able to allocate with
      msi using pci_vector_resources and some complicated accounting, and then we
      only allow each device as many irqs as we think are available on average.
      
      Only the s2io driver even takes advantage of this feature all other drivers
      have a fixed number of irqs they need and bail if they can't get them.
      
      pci_vector_resources is inaccurate if anyone ever frees an irq.  The whole
      implmentation is racy.  The current irq limit policy does not appear to make
      sense with current drivers.  So I have simplified things.  We can revisit this
      we we need a more sophisticated policy.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      92db6d10
    • E
      [PATCH] genirq: msi: refactor the msi_ops · 38bc0361
      Eric W. Biederman 提交于
      The current msi_ops are short sighted in a number of ways, this patch attempts
      to fix the glaring deficiences.
      
      - Report in msi_ops if a 64bit address is needed in the msi message, so we
        can fail 32bit only msi structures.
      
      - Send and receive a full struct msi_msg in both setup and target.  This is
        a little cleaner and allows for architectures that need to modify the data
        to retarget the msi interrupt to a different cpu.
      
      - In target pass in the full cpu mask instead of just the first cpu in case
        we can make use of the full cpu mask.
      
      - Operate in terms of irqs and not vectors, currently there is still a 1-1
        relationship but on architectures other than ia64 I expect this will change.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      38bc0361
    • E
      [PATCH] genirq: msi: implement helper functions read_msi_msg and write_msi_msg · 0366f8f7
      Eric W. Biederman 提交于
      In support of this I also add a struct msi_msg that captures the the two
      address and one data field ina typical msi message, and I remember the pos and
      if the address is 64bit in struct msi_desc.
      
      This makes the code a little more readable and easier to maintain, and paves
      the way to further simplfications.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      0366f8f7
    • E
      [PATCH] genirq: msi: simplify msi enable and disable · 7bd007e4
      Eric W. Biederman 提交于
      The problem.  Because the disable routines leave the msi interrupts in all
      sorts of half enabled states the enable routines become impossible to
      implement correctly, and almost impossible to understand.
      
      Simplifing this allows me to simply kill the buggy reroute_msix_table, and
      generally makes the code more maintainable.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      7bd007e4
  5. 27 9月, 2006 2 次提交
  6. 13 7月, 2006 1 次提交
  7. 01 7月, 2006 1 次提交
  8. 30 6月, 2006 1 次提交
    • I
      [PATCH] genirq: rename desc->handler to desc->chip · d1bef4ed
      Ingo Molnar 提交于
      This patch-queue improves the generic IRQ layer to be truly generic, by adding
      various abstractions and features to it, without impacting existing
      functionality.
      
      While the queue can be best described as "fix and improve everything in the
      generic IRQ layer that we could think of", and thus it consists of many
      smaller features and lots of cleanups, the one feature that stands out most is
      the new 'irq chip' abstraction.
      
      The irq-chip abstraction is about describing and coding and IRQ controller
      driver by mapping its raw hardware capabilities [and quirks, if needed] in a
      straightforward way, without having to think about "IRQ flow"
      (level/edge/etc.) type of details.
      
      This stands in contrast with the current 'irq-type' model of genirq
      architectures, which 'mixes' raw hardware capabilities with 'flow' details.
      The patchset supports both types of irq controller designs at once, and
      converts i386 and x86_64 to the new irq-chip design.
      
      As a bonus side-effect of the irq-chip approach, chained interrupt controllers
      (master/slave PIC constructs, etc.) are now supported by design as well.
      
      The end result of this patchset intends to be simpler architecture-level code
      and more consolidation between architectures.
      
      We reused many bits of code and many concepts from Russell King's ARM IRQ
      layer, the merging of which was one of the motivations for this patchset.
      
      This patch:
      
      rename desc->handler to desc->chip.
      
      Originally i did not want to do this, because it's a big patch.  But having
      both "desc->handler", "desc->handle_irq" and "action->handler" caused a
      large degree of confusion and made the code appear alot less clean than it
      truly is.
      
      I have also attempted a dual approach as well by introducing a
      desc->chip alias - but that just wasnt robust enough and broke
      frequently.
      
      So lets get over with this quickly.  The conversion was done automatically
      via scripts and converts all the code in the kernel.
      
      This renaming patch is the first one amongst the patches, so that the
      remaining patches can stay flexible and can be merged and split up
      without having some big monolithic patch act as a merge barrier.
      
      [akpm@osdl.org: build fix]
      [akpm@osdl.org: another build fix]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      d1bef4ed
  9. 22 6月, 2006 7 次提交
  10. 28 4月, 2006 1 次提交
  11. 15 4月, 2006 1 次提交
  12. 24 3月, 2006 4 次提交
  13. 01 2月, 2006 2 次提交
  14. 11 11月, 2005 1 次提交
    • A
      [PATCH] PCI: Change MSI to use physical delivery mode always · b4033c17
      Ashok Raj 提交于
      MSI hardcoded delivery mode to use logical delivery mode. Recently
      x86_64 moved to use physical mode addressing to support physflat mode.
      With this mode enabled noticed that my eth with MSI werent working.
      
      msi_address_init()  was hardcoded to use logical mode for i386 and x86_64.
      So when we switch to use physical mode, things stopped working.
      
      Since anyway we dont use lowest priority delivery with MSI, its always
      directed to just a single CPU. Its safe  and simpler to use
      physical mode always, even when we use logical delivery mode for IPI's
      or other ioapic RTE's.
      Signed-off-by: NAshok Raj <ashok.raj@intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      b4033c17
  15. 29 10月, 2005 1 次提交
  16. 09 9月, 2005 1 次提交