- 20 7月, 2021 18 次提交
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由 Xinhao Liu 提交于
mainline inclusion from mainline-v5.11-rc1 commit 62f3b70e category: bugfix bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=62f3b70ed656640ecb63432014f4bb258cb1975a ---------------------------------------------------------------------- There is no need to initialize some variable because they will be assigned with a value later. Link: https://lore.kernel.org/r/1607650657-35992-9-git-send-email-liweihang@huawei.comSigned-off-by: NXinhao Liu <liuxinhao5@hisilicon.com> Signed-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Lang Cheng 提交于
mainline inclusion from mainline-v5.11-rc1 commit dc93a0d9 category: bugfix bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=dc93a0d987fcfe93b132871e72d4ea5aff36dd5c ---------------------------------------------------------------------- Just format the code without modifying anything, including fixing some redundant and missing blanks and spaces and changing the variable definition order. Link: https://lore.kernel.org/r/1607650657-35992-8-git-send-email-liweihang@huawei.comSigned-off-by: NLang Cheng <chenglang@huawei.com> Signed-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Yixian Liu 提交于
mainline inclusion from mainline-v5.11-rc1 commit 29b52027 category: bugfix bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=29b52027ac354f2a0e5c4d17ca1b621a1644949d ---------------------------------------------------------------------- As the qp access right is checked and setted in common function hns_roce_v2_set_opt_fields(), there is no need to set again for a special case INIT2INIT. Fixes: 926a01dc ("RDMA/hns: Add QP operations support for hip08 SoC") Fixes: 7db82697 ("RDMA/hns: Add support for extended atomic in userspace") Link: https://lore.kernel.org/r/1607650657-35992-7-git-send-email-liweihang@huawei.comSigned-off-by: NYixian Liu <liuyixian@huawei.com> Signed-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Weihang Li 提交于
mainline inclusion from mainline-v5.11-rc1 commit f7550683 category: bugfix bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f75506833eed65cc537293508b7edd5788d67e23 ---------------------------------------------------------------------- According to the RoCE v1 specification, the sl (service level) 0-7 are mapped directly to priorities 0-7 respectively, sl 8-15 are reserved. The driver should verify whether the value of sl is larger than 7, if so, an exception should be returned. Link: https://lore.kernel.org/r/1607650657-35992-6-git-send-email-liweihang@huawei.comSigned-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Weihang Li 提交于
mainline inclusion from mainline-v5.11-rc1 commit 53ef4999 category: bugfix bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=53ef4999f07d9c75cdc8effb0cc8c581dc39b1a1 ---------------------------------------------------------------------- These flags will be returned to the userspace through ABI, so they should be defined in hns-abi.h. Furthermore, there is no need to include hns-abi.h in every source files, it just needs to be included in the common header file. Link: https://lore.kernel.org/r/1606872560-17823-1-git-send-email-liweihang@huawei.comReported-by: Nkernel test robot <lkp@intel.com> Signed-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Weihang Li 提交于
mainline inclusion from mainline-v5.11-rc1 commit 05201e01 category: bugfix bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=05201e01be937be47e4c970c0a9eb6b6fb375b1e ---------------------------------------------------------------------- The variable 'cnt' is used to represent the max number of sge an SQ WQE can use at first, then it means how many extended sge an SQ has. In addition, this function has no need to return a value. So refactor and encapsulate the parts of getting number of extended sge a WQE can use to make it easier to understand. Link: https://lore.kernel.org/r/1606558959-48510-4-git-send-email-liweihang@huawei.comSigned-off-by: NWeihang Li <liweihang@huawei.com> Reviewed-by: NLeon Romanovsky <leonro@nvidia.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Lang Cheng 提交于
mainline inclusion from mainline-v5.11-rc1 commit f93c39bc category: feature bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f93c39bc95472dae3b5de71da5c005f47ece3148 ---------------------------------------------------------------------- Stash is a mechanism that uses the core information carried by the ARM AXI bus to access the L3 cache. It can be used to improve the performance by increasing the hit ratio of L3 cache. QPs need to enable stash by default. Link: https://lore.kernel.org/r/1606374251-21512-3-git-send-email-liweihang@huawei.comSigned-off-by: NLang Cheng <chenglang@huawei.com> Signed-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Lang Cheng 提交于
mainline inclusion from mainline-v5.11-rc1 commit bfefae9f category: feature bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bfefae9f108dfa62eb9c16c9e97086fddb4ece04 ---------------------------------------------------------------------- Stash is a mechanism that uses the core information carried by the ARM AXI bus to access the L3 cache. It can be used to improve the performance by increasing the hit ratio of L3 cache. CQs need to enable stash by default. Link: https://lore.kernel.org/r/1606374251-21512-2-git-send-email-liweihang@huawei.comSigned-off-by: NLang Cheng <chenglang@huawei.com> Signed-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Yangyang Li 提交于
mainline inclusion from mainline-v5.11-rc1 commit 71586dd2 category: feature bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=71586dd2001087e89e344e2c7dcee6b4a53bb6de ---------------------------------------------------------------------- In order to improve performance by balancing the load between different banks of cache, the QPC cache is desigend to choose one of 8 banks according to lower 3 bits of QPN. The hns driver needs to count the number of QP on each bank and then assigns the QP being created to the bank with the minimum load first. Link: https://lore.kernel.org/r/1606220649-1465-1-git-send-email-liweihang@huawei.comSigned-off-by: NYangyang Li <liyangyang20@huawei.com> Signed-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Weihang Li 提交于
mainline inclusion from mainline-v5.11-rc1 commit 66d86e52 category: feature bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=66d86e529dd58616495ea0b03cc687e5d6522b59 ---------------------------------------------------------------------- HIP09 supports service type of Unreliable Datagram, add necessary process to enable this feature. Link: https://lore.kernel.org/r/1605526408-6936-7-git-send-email-liweihang@huawei.comSigned-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 wangsirong 提交于
mainline inclusion from mainline-v5.11-rc1 commit 534c9bdb category: feature bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=534c9bdb025b68b6c575fbc15976b4470e032691 ---------------------------------------------------------------------- There are some codes can be simplified or encapsulated in set_ud_wqe() to make them easier to be understand. Link: https://lore.kernel.org/r/1605526408-6936-6-git-send-email-liweihang@huawei.comSigned-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Weihang Li 提交于
mainline inclusion from mainline-v5.11-rc1 commit 148f904c category: feature bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=148f904c6f94cbd9067008142268524a95320dde ---------------------------------------------------------------------- This field in UD WQE in not used by hardware. Fixes: 7bdee415 ("RDMA/hns: Fill sq wqe context of ud type in hip08") Link: https://lore.kernel.org/r/1605526408-6936-5-git-send-email-liweihang@huawei.comSigned-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Xi Wang 提交于
mainline inclusion from mainline-v5.11-rc1 commit 6f6e2dcb category: bugfix bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6f6e2dcbb82b9b2ea304fe32635789fedd4e9868 ---------------------------------------------------------------------- Add a group of flags to control the 'struct hns_roce_buf' allocation flow, this is used to support the caller running in atomic context. Link: https://lore.kernel.org/r/1605347916-15964-1-git-send-email-liweihang@huawei.comSigned-off-by: NXi Wang <wangxi11@huawei.com> Signed-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Lang Cheng 提交于
mainline inclusion from mainline-v5.11-rc1 commit 31e2daa1 category: feature bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=31e2daa17ed9684e73a1e8e5080b70b0230bf59a ---------------------------------------------------------------------- The 200G device has a new device ID 0xA228, add it to the PCI table. Link: https://lore.kernel.org/r/1605187184-26079-1-git-send-email-liweihang@huawei.comSigned-off-by: NLang Cheng <chenglang@huawei.com> Signed-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 wangsirong 提交于
mainline inclusion from mainline-v5.11-rc1 commit aba457ca category: feature bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=aba457ca890c6a8042ba941a71129337b858d993 ---------------------------------------------------------------------- The doorbell needs to store PI information into QPC, so the RoCEE should wait for the results of storing, that is, it needs two bus operations to complete a doorbell. When ROCEE is in SDI mode, multiple doorbells may be interlocked because the RoCEE can only handle bus operations serially. So a flag to mark if HIP09 is working in SDI mode is added. When the SDI flag is set, the ROCEE will ignore the PI information of the doorbell, continue to fetch wqe and verify its validity by it's owner_bit. Link: https://lore.kernel.org/r/1603195493-22741-1-git-send-email-liweihang@huawei.comSigned-off-by: NLang Cheng <chenglang@huawei.com> Signed-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Weihang Li 提交于
mainline inclusion from mainline-v5.11-rc1 commit 7af80c02 category: bugfix bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7af80c02c7b3cf7ac580a33f15d155730574769f ---------------------------------------------------------------------- A return statement is omitted after getting HEM table, then the newly allocated pointer will be freed directly, which will cause a calltrace when the driver was removed. Fixes: d6d91e46 ("RDMA/hns: Add support for configuring GMV table") Link: https://lore.kernel.org/r/1605180582-46504-1-git-send-email-liweihang@huawei.comSigned-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Weihang Li 提交于
mainline inclusion from mainline-v5.11-rc1 commit 32053e58 category: feature bugzilla: 174002 CVE:NA Reference:https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=32053e584e4a342be37a0932ffc1f9b13e914515 ---------------------------------------------------------------------- Add a interface to fill GMV(SGID/SMAC/VLAN) table for HIP09, all of above source address information is stored as an entry in GMV table. The users just need to provide the index to the hardware when POST SEND. Link: https://lore.kernel.org/r/1603508836-33054-3-git-send-email-liweihang@huawei.comSigned-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 wangsirong 提交于
mainline inclusion from mainline-v5.11-rc1 commit d6d91e46 category: feature bugzilla: 174002 CVE:NA Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d6d91e46210f3adb7b6d4c667cb72bf847b5783a ---------------------------------------------------------------------- HIP09 supports to store SGID/SMAC/VLAN together in a table named GMV. The driver needs to allocate memory for it and tell the information about this region to hardware. Link: https://lore.kernel.org/r/1603508836-33054-2-git-send-email-liweihang@huawei.comSigned-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: Nwangsirong <wangsirong@huawei.com> Reviewed-by: NChunZhi Hu <huchunzhi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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- 03 7月, 2021 2 次提交
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由 Alaa Hleihel 提交于
stable inclusion from stable-5.10.44 commit 91f7fdc4cc10542ca1045c06aad23365f0d067e0 bugzilla: 109295 CVE: NA -------------------------------- commit 2ba0aa2f upstream. The function init_cq_frag_buf() can be called to initialize the current CQ fragments buffer cq->buf, or the temporary cq->resize_buf that is filled during CQ resize operation. However, the offending commit started to use function get_cqe() for getting the CQEs, the issue with this change is that get_cqe() always returns CQEs from cq->buf, which leads us to initialize the wrong buffer, and in case of enlarging the CQ we try to access elements beyond the size of the current cq->buf and eventually hit a kernel panic. [exception RIP: init_cq_frag_buf+103] [ffff9f799ddcbcd8] mlx5_ib_resize_cq at ffffffffc0835d60 [mlx5_ib] [ffff9f799ddcbdb0] ib_resize_cq at ffffffffc05270df [ib_core] [ffff9f799ddcbdc0] llt_rdma_setup_qp at ffffffffc0a6a712 [llt] [ffff9f799ddcbe10] llt_rdma_cc_event_action at ffffffffc0a6b411 [llt] [ffff9f799ddcbe98] llt_rdma_client_conn_thread at ffffffffc0a6bb75 [llt] [ffff9f799ddcbec8] kthread at ffffffffa66c5da1 [ffff9f799ddcbf50] ret_from_fork_nospec_begin at ffffffffa6d95ddd Fix it by getting the needed CQE by calling mlx5_frag_buf_get_wqe() that takes the correct source buffer as a parameter. Fixes: 388ca8be ("IB/mlx5: Implement fragmented completion queue (CQ)") Link: https://lore.kernel.org/r/90a0e8c924093cfa50a482880ad7e7edb73dc19a.1623309971.git.leonro@nvidia.comSigned-off-by: NAlaa Hleihel <alaa@nvidia.com> Signed-off-by: NLeon Romanovsky <leonro@nvidia.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Shay Drory 提交于
stable inclusion from stable-5.10.44 commit cb1aa1da04882d1860f733e24aeebdbbc85724d7 bugzilla: 109295 CVE: NA -------------------------------- commit 404e5a12 upstream. Currently when mlx4 maps the hca_core_clock page to the user space there are read-modifiable registers, one of which is semaphore, on this page as well as the clock counter. If user reads the wrong offset, it can modify the semaphore and hang the device. Do not map the hca_core_clock page to the user space unless the device has been put in a backwards compatibility mode to support this feature. After this patch, mlx4 core_clock won't be mapped to user space on the majority of existing devices and the uverbs device time feature in ibv_query_rt_values_ex() will be disabled. Fixes: 52033cfb ("IB/mlx4: Add mmap call to map the hardware clock") Link: https://lore.kernel.org/r/9632304e0d6790af84b3b706d8c18732bc0d5e27.1622726305.git.leonro@nvidia.comSigned-off-by: NShay Drory <shayd@nvidia.com> Signed-off-by: NLeon Romanovsky <leonro@nvidia.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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- 03 6月, 2021 12 次提交
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由 Maor Gottlieb 提交于
stable inclusion from stable-5.10.40 commit c62c907ccc63b5ba59609ceecda1b04998d41962 bugzilla: 51882 CVE: NA -------------------------------- [ Upstream commit cfa3b797 ] When executing DEVX command to query QP object, we need to take the QP type from the mlx5_ib_qp struct which hold the driver specific QP types as well, such as DC. Fixes: 34613eb1 ("IB/mlx5: Enable modify and query verbs objects via DEVX") Link: https://lore.kernel.org/r/6eee15d63f09bb70787488e0cf96216e2957f5aa.1621413654.git.leonro@nvidia.comReviewed-by: NYishai Hadas <yishaih@nvidia.com> Signed-off-by: NMaor Gottlieb <maorg@nvidia.com> Signed-off-by: NLeon Romanovsky <leonro@nvidia.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Maor Gottlieb 提交于
stable inclusion from stable-5.10.40 commit 75bdfe7837322788eca2aa321f6160e35361ff41 bugzilla: 51882 CVE: NA -------------------------------- [ Upstream commit 97f30d32 ] When there is fatal event on the slave port, the device is marked as not active. We need to mark it as active again when the slave is recovered to regain full functionality. Fixes: d69a24e0 ("IB/mlx5: Move IB event processing onto a workqueue") Link: https://lore.kernel.org/r/8906754455bb23019ef223c725d2c0d38acfb80b.1620711734.git.leonro@nvidia.comSigned-off-by: NMaor Gottlieb <maorg@nvidia.com> Signed-off-by: NLeon Romanovsky <leonro@nvidia.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Mike Marciniszyn 提交于
stable inclusion from stable-5.10.38 commit 437a4746e47e17bbc7b33931187528514ad9e1aa bugzilla: 51875 CVE: NA -------------------------------- [ Upstream commit b536d4b2 ] The completion ring for tx is using the wrong size to size the ring, oversizing the ring by two orders of magniture. Correct the allocation size and use kcalloc_node() to allocate the ring. Fix mistaken GFP defines in similar allocations. Link: https://lore.kernel.org/r/1617026056-50483-4-git-send-email-dennis.dalessandro@cornelisnetworks.comReviewed-by: NKaike Wan <kaike.wan@intel.com> Signed-off-by: NMike Marciniszyn <mike.marciniszyn@cornelisnetworks.com> Signed-off-by: NDennis Dalessandro <dennis.dalessandro@cornelisnetworks.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Lv Yunlong 提交于
stable inclusion from stable-5.10.37 commit f5ce59707d6a26ed98061d0640a0eaf8e7125bdc bugzilla: 51868 CVE: NA -------------------------------- [ Upstream commit 34b39efa ] In bnxt_qplib_alloc_res, it calls bnxt_qplib_alloc_dpi_tbl(). Inside bnxt_qplib_alloc_dpi_tbl, dpit->dbr_bar_reg_iomem is freed via pci_iounmap() in unmap_io error branch. After the callee returns err code, bnxt_qplib_alloc_res calls bnxt_qplib_free_res()->bnxt_qplib_free_dpi_tbl() in the fail branch. Then dpit->dbr_bar_reg_iomem is freed in the second time by pci_iounmap(). My patch set dpit->dbr_bar_reg_iomem to NULL after it is freed by pci_iounmap() in the first time, to avoid the double free. Fixes: 1ac5a404 ("RDMA/bnxt_re: Add bnxt_re RoCE driver") Link: https://lore.kernel.org/r/20210426140614.6722-1-lyl2019@mail.ustc.edu.cnSigned-off-by: NLv Yunlong <lyl2019@mail.ustc.edu.cn> Reviewed-by: NLeon Romanovsky <leonro@nvidia.com> Acked-by: NDevesh Sharma <devesh.sharma@broadcom.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Sindhu Devale 提交于
stable inclusion from stable-5.10.37 commit 312c5ce349426ad4771571ce0442f31a4045184d bugzilla: 51868 CVE: NA -------------------------------- [ Upstream commit 783a11bf ] When i40iw_hmc_sd_one fails, chunk is freed without the deletion of chunk entry in the PBLE info list. Fix it by adding the chunk entry to the PBLE info list only after successful addition of SD in i40iw_hmc_sd_one. This fixes a static checker warning reported here: https://lore.kernel.org/linux-rdma/YHV4CFXzqTm23AOZ@mwanda/ Fixes: 97158301 ("i40iw: add pble resource files") Link: https://lore.kernel.org/r/20210416002104.323-1-shiraz.saleem@intel.comReported-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NSindhu Devale <sindhu.devale@intel.com> Signed-off-by: NShiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Potnuri Bharat Teja 提交于
stable inclusion from stable-5.10.37 commit 45b84abb47a9c7d05d046e93e8a3769ebee25dfa bugzilla: 51868 CVE: NA -------------------------------- [ Upstream commit 3a668438 ] missing qpid increment leads to skipping few qpids while allocating QP. This eventually leads to adapter running out of qpids after establishing fewer connections than it actually supports. Current patch increments the qpid correctly. Fixes: cfdda9d7 ("RDMA/cxgb4: Add driver for Chelsio T4 RNIC") Link: https://lore.kernel.org/r/20210415151422.9139-1-bharat@chelsio.comSigned-off-by: NPotnuri Bharat Teja <bharat@chelsio.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Wang Wensheng 提交于
stable inclusion from stable-5.10.37 commit 52fd8005a2391ad88587ec79536e9cceb3d899cb bugzilla: 51868 CVE: NA -------------------------------- [ Upstream commit 22efb0a8 ] Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: 1ac5a404 ("RDMA/bnxt_re: Add bnxt_re RoCE driver") Link: https://lore.kernel.org/r/20210408113137.97202-1-wangwensheng4@huawei.comReported-by: NHulk Robot <hulkci@huawei.com> Signed-off-by: NWang Wensheng <wangwensheng4@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Wang Wensheng 提交于
stable inclusion from stable-5.10.37 commit afb738b74447966912c55bc620caa2811f200292 bugzilla: 51868 CVE: NA -------------------------------- [ Upstream commit 4c7d9c69 ] Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: 77241056 ("IB/hfi1: add driver files") Link: https://lore.kernel.org/r/20210408113140.103032-1-wangwensheng4@huawei.comReported-by: NHulk Robot <hulkci@huawei.com> Signed-off-by: NWang Wensheng <wangwensheng4@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Wang Wensheng 提交于
stable inclusion from stable-5.10.37 commit a12d75f5dcfbeb0557c79b036c780606dce99d60 bugzilla: 51868 CVE: NA -------------------------------- [ Upstream commit 10dd83db ] Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: 82af6d19 ("RDMA/qedr: Fix synchronization methods and memory leaks in qedr") Link: https://lore.kernel.org/r/20210408113135.92165-1-wangwensheng4@huawei.comReported-by: NHulk Robot <hulkci@huawei.com> Signed-off-by: NWang Wensheng <wangwensheng4@huawei.com> Acked-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Mike Marciniszyn 提交于
stable inclusion from stable-5.10.37 commit 8fac4bd3674ffdb85f835cf497888fbb913e40a3 bugzilla: 51868 CVE: NA -------------------------------- [ Upstream commit ca5f7256 ] The code currently assumes that the mmu_notifier struct embedded in mmu_rb_handler only contains two fields. There are now extra fields: struct mmu_notifier { struct hlist_node hlist; const struct mmu_notifier_ops *ops; struct mm_struct *mm; struct rcu_head rcu; unsigned int users; }; Given that there in no init for the mmu_notifier, a kzalloc() should be used to insure that any newly added fields are given a predictable initial value of zero. Fixes: 06e0ffa6 ("IB/hfi1: Re-factor MMU notification code") Link: https://lore.kernel.org/r/1617026056-50483-9-git-send-email-dennis.dalessandro@cornelisnetworks.comReviewed-by: NAdam Goldman <adam.goldman@intel.com> Signed-off-by: NMike Marciniszyn <mike.marciniszyn@cornelisnetworks.com> Signed-off-by: NDennis Dalessandro <dennis.dalessandro@cornelisnetworks.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Maor Gottlieb 提交于
stable inclusion from stable-5.10.37 commit 78f537c0054a485d4e3dfb69866e2611a4bcc5c9 bugzilla: 51868 CVE: NA -------------------------------- [ Upstream commit c7370080 ] Initial drop action support missed that drop action can be added to egress flow tables as well. Add the missing support. This requires making sure that dest_type isn't set to PORT which in turn exposes a possibility of passing dst while indicating number of dsts as zero. Explicitly check for number of dsts and pass the appropriate pointer. Fixes: f29de9ee ("RDMA/mlx5: Add support for drop action in DV steering") Link: https://lore.kernel.org/r/20210318135123.680759-1-leon@kernel.orgReviewed-by: NMark Bloch <markb@nvidia.com> Signed-off-by: NMaor Gottlieb <maorg@nvidia.com> Signed-off-by: NLeon Romanovsky <leonro@nvidia.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Mark Zhang 提交于
stable inclusion from stable-5.10.37 commit 0d74db1457872be4e272652996a7d86c07f20e76 bugzilla: 51868 CVE: NA -------------------------------- [ Upstream commit 6fe6e568 ] Correct the map between mlx5 rates and corresponding ib rates, as they don't always have a fixed offset between them. Fixes: e126ba97 ("mlx5: Add driver for Mellanox Connect-IB adapters") Link: https://lore.kernel.org/r/20210304124517.1100608-4-leon@kernel.orgSigned-off-by: NMark Zhang <markzhang@nvidia.com> Reviewed-by: NMaor Gottlieb <maorg@nvidia.com> Signed-off-by: NLeon Romanovsky <leonro@nvidia.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NWeilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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- 26 4月, 2021 3 次提交
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由 Kamal Heib 提交于
stable inclusion from stable-5.10.30 commit d8a0861e269d583f6420bed104866d2dc69c2711 bugzilla: 51791 -------------------------------- [ Upstream commit e1ad897b ] As INI QP does not require a recv_cq, avoid the following null pointer dereference by checking if the qp_type is not INI before trying to extract the recv_cq. BUG: kernel NULL pointer dereference, address: 00000000000000e0 #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not-present page PGD 0 P4D 0 Oops: 0000 [#1] SMP PTI CPU: 0 PID: 54250 Comm: mpitests-IMB-MP Not tainted 5.12.0-rc5 #1 Hardware name: Dell Inc. PowerEdge R320/0KM5PX, BIOS 2.7.0 08/19/2019 RIP: 0010:qedr_create_qp+0x378/0x820 [qedr] Code: 02 00 00 50 e8 29 d4 a9 d1 48 83 c4 18 e9 65 fe ff ff 48 8b 53 10 48 8b 43 18 44 8b 82 e0 00 00 00 45 85 c0 0f 84 10 74 00 00 <8b> b8 e0 00 00 00 85 ff 0f 85 50 fd ff ff e9 fd 73 00 00 48 8d bd RSP: 0018:ffff9c8f056f7a70 EFLAGS: 00010202 RAX: 0000000000000000 RBX: ffff9c8f056f7b58 RCX: 0000000000000009 RDX: ffff8c41a9744c00 RSI: ffff9c8f056f7b58 RDI: ffff8c41c0dfa280 RBP: ffff8c41c0dfa280 R08: 0000000000000002 R09: 0000000000000001 R10: 0000000000000000 R11: ffff8c41e06fc608 R12: ffff8c4194052000 R13: 0000000000000000 R14: ffff8c4191546070 R15: ffff8c41c0dfa280 FS: 00007f78b2787b80(0000) GS:ffff8c43a3200000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00000000000000e0 CR3: 00000001011d6002 CR4: 00000000001706f0 Call Trace: ib_uverbs_handler_UVERBS_METHOD_QP_CREATE+0x4e4/0xb90 [ib_uverbs] ? ib_uverbs_cq_event_handler+0x30/0x30 [ib_uverbs] ib_uverbs_run_method+0x6f6/0x7a0 [ib_uverbs] ? ib_uverbs_handler_UVERBS_METHOD_QP_DESTROY+0x70/0x70 [ib_uverbs] ? __cond_resched+0x15/0x30 ? __kmalloc+0x5a/0x440 ib_uverbs_cmd_verbs+0x195/0x360 [ib_uverbs] ? xa_load+0x6e/0x90 ? cred_has_capability+0x7c/0x130 ? avc_has_extended_perms+0x17f/0x440 ? vma_link+0xae/0xb0 ? vma_set_page_prot+0x2a/0x60 ? mmap_region+0x298/0x6c0 ? do_mmap+0x373/0x520 ? selinux_file_ioctl+0x17f/0x220 ib_uverbs_ioctl+0xa7/0x110 [ib_uverbs] __x64_sys_ioctl+0x84/0xc0 do_syscall_64+0x33/0x40 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7f78b120262b Fixes: 06e8d1df ("RDMA/qedr: Add support for user mode XRC-SRQ's") Link: https://lore.kernel.org/r/20210404125501.154789-1-kamalheib1@gmail.comSigned-off-by: NKamal Heib <kamalheib1@gmail.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: N Weilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Potnuri Bharat Teja 提交于
stable inclusion from stable-5.10.30 commit 7f40e93328989279fee7a718736c386c13d44aa8 bugzilla: 51791 -------------------------------- [ Upstream commit 603c4690 ] ipv6 bit is wrongly set by the below which causes fatal adapter lookup engine errors for ipv4 connections while destroying a listener. Fix it to properly check the local address for ipv6. Fixes: 3408be14 ("RDMA/cxgb4: Fix adapter LE hash errors while destroying ipv6 listening server") Link: https://lore.kernel.org/r/20210331135715.30072-1-bharat@chelsio.comSigned-off-by: NPotnuri Bharat Teja <bharat@chelsio.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: N Weilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Mike Marciniszyn 提交于
stable inclusion from stable-5.10.30 commit de427b662bfb23546cd0af4af86c8b945e780755 bugzilla: 51791 -------------------------------- commit 5de61a47 upstream. A panic can result when AIP is enabled: BUG: unable to handle kernel NULL pointer dereference at 000000000000000 PGD 0 P4D 0 Oops: 0000 1 SMP PTI CPU: 70 PID: 981 Comm: systemd-udevd Tainted: G OE --------- - - 4.18.0-240.el8.x86_64 #1 Hardware name: Intel Corporation S2600KP/S2600KP, BIOS SE5C610.86B.01.01.0005.101720141054 10/17/2014 RIP: 0010:__bitmap_and+0x1b/0x70 RSP: 0018:ffff99aa0845f9f0 EFLAGS: 00010246 RAX: 0000000000000000 RBX: ffff8d5a6fc18000 RCX: 0000000000000048 RDX: 0000000000000000 RSI: ffffffffc06336f0 RDI: ffff8d5a8fa67750 RBP: 0000000000000079 R08: 0000000fffffffff R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000001 R12: ffffffffc06336f0 R13: 00000000000000a0 R14: ffff8d5a6fc18000 R15: 0000000000000003 FS: 00007fec137a5980(0000) GS:ffff8d5a9fa80000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 0000000a04b48002 CR4: 00000000001606e0 Call Trace: hfi1_num_netdev_contexts+0x7c/0x110 [hfi1] hfi1_init_dd+0xd7f/0x1a90 [hfi1] ? pci_bus_read_config_dword+0x49/0x70 ? pci_mmcfg_read+0x3e/0xe0 do_init_one.isra.18+0x336/0x640 [hfi1] local_pci_probe+0x41/0x90 pci_device_probe+0x105/0x1c0 really_probe+0x212/0x440 driver_probe_device+0x49/0xc0 device_driver_attach+0x50/0x60 __driver_attach+0x61/0x130 ? device_driver_attach+0x60/0x60 bus_for_each_dev+0x77/0xc0 ? klist_add_tail+0x3b/0x70 bus_add_driver+0x14d/0x1e0 ? dev_init+0x10b/0x10b [hfi1] driver_register+0x6b/0xb0 ? dev_init+0x10b/0x10b [hfi1] hfi1_mod_init+0x1e6/0x20a [hfi1] do_one_initcall+0x46/0x1c3 ? free_unref_page_commit+0x91/0x100 ? _cond_resched+0x15/0x30 ? kmem_cache_alloc_trace+0x140/0x1c0 do_init_module+0x5a/0x220 load_module+0x14b4/0x17e0 ? __do_sys_finit_module+0xa8/0x110 __do_sys_finit_module+0xa8/0x110 do_syscall_64+0x5b/0x1a0 The issue happens when pcibus_to_node() returns NO_NUMA_NODE. Fix this issue by moving the initialization of dd->node to hfi1_devdata allocation and remove the other pcibus_to_node() calls in the probe path and use dd->node instead. Affinity logic is adjusted to use a new field dd->affinity_entry as a guard instead of dd->node. Fixes: 4730f4a6 ("IB/hfi1: Activate the dummy netdev") Link: https://lore.kernel.org/r/1617025700-31865-4-git-send-email-dennis.dalessandro@cornelisnetworks.com Cc: stable@vger.kernel.org Signed-off-by: NMike Marciniszyn <mike.marciniszyn@cornelisnetworks.com> Signed-off-by: NDennis Dalessandro <dennis.dalessandro@cornelisnetworks.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: N Weilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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- 19 4月, 2021 1 次提交
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由 Potnuri Bharat Teja 提交于
stable inclusion from stable-5.10.27 commit d95696f537d6aef952f2611aee8cc2be1ff8fe09 bugzilla: 51493 -------------------------------- [ Upstream commit 3408be14 ] Not setting the ipv6 bit while destroying ipv6 listening servers may result in potential fatal adapter errors due to lookup engine memory hash errors. Therefore always set ipv6 field while destroying ipv6 listening servers. Fixes: 830662f6 ("RDMA/cxgb4: Add support for active and passive open connection with IPv6 address") Link: https://lore.kernel.org/r/20210324190453.8171-1-bharat@chelsio.comSigned-off-by: NPotnuri Bharat Teja <bharat@chelsio.com> Reviewed-by: NLeon Romanovsky <leonro@nvidia.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: N Weilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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- 14 4月, 2021 1 次提交
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由 Xi Wang 提交于
driver inclusion category: bugfix bugzilla: 50786 ------------------------------ The base address table is allocated by dma allocator, and the size is always aligned to PAGE_SIZE. If use the fixed size to allocated the table, the base address entries which stored in table will be smaller than the actual memory space can store. Signed-off-by: NXi Wang <wangxi11@huawei.com> Reviewed-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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- 13 4月, 2021 1 次提交
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由 Mark Bloch 提交于
stable inclusion from stable-5.10.26 commit 8b4a797e86a0fad5dcdd1c4ae71cd9bafbfa7295 bugzilla: 51363 -------------------------------- [ Upstream commit 2614488d ] The cited commit disallowed creating any QP which isn't raw ethernet, reg umr or the special UD qp for testing WC, this proved too strict. While modify can't be done (no GIDS/GID table for example) just creating a QP is okay. This patch partially reverts the bellow mentioned commit and places the restriction at the modify QP stage and not at the creation. DEVX commands should be used to manipulate such QPs. Fixes: 42caf9cb ("RDMA/mlx5: Allow only raw Ethernet QPs when RoCE isn't enabled") Link: https://lore.kernel.org/r/20210125120709.836718-1-leon@kernel.orgSigned-off-by: NMark Bloch <mbloch@nvidia.com> Reviewed-by: NMaor Gottlieb <maorg@mellanox.com> Signed-off-by: NLeon Romanovsky <leonro@nvidia.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: N Weilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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- 09 4月, 2021 2 次提交
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由 YueHaibing 提交于
stable inclusion from stable-5.10.22 commit 7ef9d23bc3121be3e77ed7fbcf9d3c9ecbf7005e bugzilla: 50796 -------------------------------- [ Upstream commit 3a9b3d45 ] Set err to -ENOMEM if kzalloc fails instead of 0. Fixes: 75973853 ("IB/mlx5: Enable subscription for device events over DEVX") Link: https://lore.kernel.org/r/20210222122343.19720-1-yuehaibing@huawei.comSigned-off-by: NYueHaibing <yuehaibing@huawei.com> Acked-by: NLeon Romanovsky <leonro@nvidia.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: N Weilong Chen <chenweilong@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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由 Lang Cheng 提交于
stable inclusion from stable-5.10.20 commit 55bfe125b44ae924ecc73b7fffaca0b6e3c30bd5 bugzilla: 50608 -------------------------------- [ Upstream commit 8f86e2ea ] When posting a multi-descriptors command, the error code of previous failed descriptors may be rewrote to 0 by a later successful descriptor. Fixes: a04ff739 ("RDMA/hns: Add command queue support for hip08 RoCE driver") Link: https://lore.kernel.org/r/1612688143-28226-3-git-send-email-liweihang@huawei.comSigned-off-by: NLang Cheng <chenglang@huawei.com> Signed-off-by: NWeihang Li <liweihang@huawei.com> Signed-off-by: NJason Gunthorpe <jgg@nvidia.com> Signed-off-by: NSasha Levin <sashal@kernel.org> Signed-off-by: NChen Jun <chenjun102@huawei.com> Acked-by: NXie XiuQi <xiexiuqi@huawei.com> Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>
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