'vtwm_pll_ops' is local to this file. Make it static.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Cc: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Current vt8500 board init calls of_clk_init() from vtwm_clk_init. To allow
consolidation of DT driven .time_init, move of_clock_init() to a temporary
.time_init callback that will be removed when arch-wide callback is available.
With previous pmc_base parsing helper for vt8500 clock providers, we can also
safely remove the call to vtwm_clk_init() and get rid of some includes.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NTony Prisk <linux@prisktech.co.nz>
Acked-by: NMike Turquette <mturquette@linaro.org>

Currently, clock providers for vt8500 depend on machine_init providing
pmc_base address before calling of_clk_init. With upcoming arch-wide
.time_init calling of_clk_init, we should make clock providers independent
of mach code. This adds a pmc_base parsing helper to current clock provider
that gets called if there is no pmc_base set, yet.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NTony Prisk <linux@prisktech.co.nz>
Acked-by: NMike Turquette <mturquette@linaro.org>

With the addition of a DVO clock, a bug is now evident in the vt8500
clock code:
[    0.290000] WARNING: at init/main.c:698 do_one_initcall+0x158/0x18c()
[    0.300000] initcall wm8505fb_driver_init+0x0/0xc returned with disabled int

This is caused by an unbalanced spinlock in vt8500_dclk_set_rate().
Replace the second call to spin_lock_irqsave() with spin_unlock_irqrestore().
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The divisor adjustment code to ensure that a divisor is not rounded down,
thereby giving a rate higher than requested, is unnecessary and in some
instances results in the actual rate being much lower than requested due to
rounding errors.

The test is already performed in vtwm_dclk_round_rate(), which is always
called when clk_set_rate is called. Due to rounding errors in the line:
divisor = parent_rate / rate (clk-vt8500.c:160) we will sometimes end up
adjusting the divisor twice - first in round_rate and then again in set_rate.

This patch removes the test/adjustment in vtwm_dclk_set_rate.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The WM8850 has a different PLL clock to the previous versions. This
patch adds support for the WM8850-style PLL clocks.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The case of PLL_TYPE_WM8750 in both these functions is missing a break
statement causing a fall-through to the default: case.

Insert the missing break statements.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Patch 72480014 "Fix device clock divisor calculations" was apparently
rebased incorrectly before it got upstream, causing a build error.

Replacing the "prate" pointer with the local parent_rate is most
likely the correct solution.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Tony Prisk <linux@prisktech.co.nz>
Cc: Mike Turquette <mturquette@linaro.org>

Use common of_clk_init() function for clock initialization.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: added entry for wm8750-pll-clock]
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds support for the new PLL module found in WM8750 and
WM8850 SoCs.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

A request to vt8500_dclk_(round_rate/set_rate) with rate=0 results
in a division-by-0 in the kernel.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

When calculating device clock divisor values in set_rate and
round_rate, we do a simple integer divide. If parent_rate / rate
has a fraction, this is dropped which results in the device clock
being set too high.

This patch corrects the problem by adding 1 to the calculated
divisor if the division would have had a decimal result.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

When a PLL frequency calculation is performed and a non-exact match
is found the wrong multiplier and divisors are returned.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds some additional handling for the SDMMC special case
in round_rate and set_rate which results in invalid divisor messages
at boot time.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds common clock framework support for arch-vt8500.
Support for PLL and device clocks on VT8500, WM8505 and WM8650
are included.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Acked-by: NMike Turquette <mturquette@linaro.org>