Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This brings the parts in line with newer ones, and makes things easier
to read at a glance.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

These files had a lot of whitespace damage, mostly due to copying and
pasting original files that had damage.

The BF561 header also had a lot of unused CONFIG_DEF_xxx defines, so
punt them all.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Start a new common IRQ header and move all of the CEC pieces there.  This
lets the individual part headers worry just about its SIC defines.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

When run kgdb testing, it looks like coreb hangs in single step or trap
exception without handling anomaly 05000257 properly on bf561 v0.5.  But,
the anomaly list says it apply to bf561 v0.4 and bellow.  Apply its work
around to 0.5 temporarily until the behavior and the root cause can be
confirmed by the hardware team.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Currently, sending an interprocessor interrupt (IPI) requires building up
a message dynamically which means memory allocation.  But often times, we
will want to send an IPI in low level contexts where allocation is not
possible which may lead to a panic().  So create a per-cpu static array
for the message queue and use that instead.

Further, while we have two supplemental interrupts, we are currently only
using one of them.  So use the second one for the most common IPI message
of all -- smp_send_reschedule().  This avoids ugly contention for locks
which in turn would require an IPI message ...

In general, this improves SMP performance, and in some cases allows the
SMP port to work in places it wouldn't before.  Such as the PREEMPT_RT
state where the slab is protected by a per-cpu spin lock.  If the slab
kmalloc/kfree were to put the task to sleep, and that task was actually
the IPI handler, then the system falls down yet again.

After running some various stress tests on the system, the static limit
of 5 messages seems to work.  On the off chance even this overflows, we
simply panic(), and we can review that scenario to see if the limit needs
to be increased a bit more.
Signed-off-by: NYi Li <yi.li@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The BF561 mem_map.h header has the __ASSEMBLY__/CONFIG_SMP checks out
of order which leads to build errors for assembly code that happens to
include this file.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This function takes an irq_handler_t function, but the prototype in
the header doesn't match the function definition.  This is due to the
smp headers needing to avoid circular dependencies.  So change the
function to take a simple pointer.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Looks like I missed a few new spots when renaming the SICA macros.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

These were only included because of the irq handling of the PLL funcs,
and those PLL funcs have been moved out into their own header now.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The main asm/blackfin.h header will pull in mach/blackfin.h to get
all the fun Blackfin defines.  So having any of the sub-mach headers
trying to include asm/blackfin.h makes no sense -- punt it.

The mach/blackfin.h header takes care of including the part-specific
def headers which in turn will include any other needed def file.
Similarly, it takes care of pulling in the part-specific cdef header.
So move this logic out of the blackfin.h when necessary.

Further, make sure the cdef headers do not waste time including the
def headers again.

Since all parts need the common def/cdef headers, move this logic
out of the part-specific headers and into the mach/blackfin.h file.

Finally, we need to split the BF539 def header since the BF538 does
not have MXVR and we don't want to expose those MMRs.

So now all parts should have the same behavior:
	mach/blackfin.h
		asm/def_LPBlackfin.h
		part-specific def.h
		if ! asm
			asm/cdef_LPBlackfin.h
			part-specific cdef.h
And the sub def/cdef headers only tail into what they need.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Use the same naming convention for DMA traffic MMRs (most were legacy
anyways) so we can avoid useless ifdef trees.

Same goes for MDMA names -- this actually allows us to undo a bunch of
ifdef redirects that existed for this purpose alone.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Each Blackfin port has been duplicating UART structures and defines when
there really is no need for it.  So start a new bfin_serial.h header to
unify all these pieces and give ourselves a fresh start.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This matches all the other Blackfin ports and keep us from having to write
bf561-specific code in many places.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Now that the common header defines everything and the SPI drivers are
using it, we can drop these duplicated global namespace polluters.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Rename h/w IRQ flags handling functions to be in line with what is expected for
the irq renaming patch.  This renames local_*_hw() to hard_local_*() using the
following perl command:

	perl -pi -e 's/local_irq_(restore|enable|disable)_hw/hard_local_irq_\1/ or s/local_irq_save_hw([_a-z]*)[(]flags[)]/flags = hard_local_irq_save\1()/' `find arch/blackfin/ -name "*.[ch]"`

and then fixing up asm/irqflags.h manually.

Additionally, arch/hard_local_save_flags() and arch/hard_local_irq_save() both
return the flags rather than passing it through the argument list.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Split the PLL control code from the Blackfin machine-specific cdef headers so
that the irqflags functions can be renamed without incurring a header loop.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

The common bfin_sport.h header now has unified definitions of these, so
stop polluting the global namespace.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Random tabs instead of spaces, mixes of the two, and unicode spaces
instead of ascii spaces.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This is parallel to the existing P_DEFAULT_BOOT_SPI_CS, but in terms of
the GPIO value so it can be used with the normal gpio API.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This makes room for off-chip IRQ controllers.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

SMP systems require per-cpu local clock event devices in order to enable
HRT support.  One a BF561, we can use local core timer for this purpose.
Originally, there was one global core-timer clock event device set up for
core A.

To accomplish this feat, we need to split the gptimer0/core timer logic
so that each is a standalone clock event.  There is no requirement that
we only have one clock event source anyways.  Once we have this, we just
define per-cpu clock event devices for each local core timer.
Signed-off-by: NYi Li <yi.li@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Every Blackfin variant has the same DMA bit masks, so avoid duplicating
them over and over in each mach header.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Add some recently documented anomalies (473, 474, 475, 477).  Also stick
a "do not edit" notice in here so people know these are copies of some
master version.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Bill Gatliff & David Brownell pointed out we were missing some
copyrights, and licensing terms in some of the files in
./arch/blackfin, so this fixes things, and cleans them up.

It also removes:
 - verbose GPL text(refer to the top level ./COPYING file)
 - file names (you are looking at the file)
 - bug url (it's in the ./MAINTAINERS file)
 - "or later" on GPL-2, when we did not have that right

It also allows some Blackfin-specific assembly files to be under a BSD
like license (for people to use them outside of Linux).
Signed-off-by: NRobin Getz <robin.getz@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NYi Li <yi.li@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The Blackfin serial headers were inverting the CTS value leading to wrong
handling of the CTS line which broke CTS/RTS handling completely.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The Blackfin serial headers were inverting the CTS value leading to wrong
handling of the CTS line which broke CTS/RTS handling completely.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Rather than assume Core B is always run with caches turned on, let people
load into any of the on-chip memory regions.  It is their business how the
SRAM/Cache regions are utilized, so don't prevent them from being able to
load into them.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NCliff Cai <cliff.cai@analog.com>
Signed-off-by: NRobin Getz <robin.getz@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Many aspects of the Blackfin memory map is exactly the same across all
variants.  Rather than copy and paste all of these duplicated values in
each header, unify all of these into the common Blackfin memory map header
file.  In the process, push down BF561 SMP specific stuff to the BF561
specific header to keep the noise down.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Update anomaly headers to match latest released anomaly sheets.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Add some defines to make the BF538/BF561 look like most other Blackfin
parts in that it has a MDMA0 channel available for low level init.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Signed-off-by: NBryan Wu <cooloney@kernel.org>

Both software emulated and hardware based CTS and RTS are enabled in
serial driver.

The CTS RTS PIN connection on BF548 UART port is defined as a modem
device not as a host device.  In order to test it under Linux, please
nake a cross UART cable to exchange CTS and RTS signal.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NBryan Wu <cooloney@kernel.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NAlan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>