get_page_entry calculates the GART page table entry, which is just written
to the GART page table by set_page_entry.

This is a prerequisite for the following fix.
Reviewed-by: NChristian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This was accidently lost in 76a0df85.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

It was causing display corruption with R300 generation GPUs at least.
Reported-and-Tested-by: NMikael Pettersson <mikpelinux@gmail.com>
Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Don't enable UVD on these asics as they don't have
UVD hardware.
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v2: cleanup R600 support
v3: rebased on current drm-fixes-3.12
v4: rebased on drm-next-3.14
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Move the decision what to use into the common VM code.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:

* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
  is performed via MMIO
Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

And clean up the function comment a little.
Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This needs some tweaking to be stable with newer
ucode versions.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The underlying reason for the crashes seems to be fixed now.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

They are doing the same on all generations anyway.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

DCE 3.1 and 3.2 should be programmed in a different way than DCE 2 and
DCE 3. The order of setting registers and sets of registers are
different.
It's still unsure how we will handle DCE 3.1 vs. DCE 3.2, since they
have few differences as well.
For now separate DCE 2 and DCE 3 path, so we can work on it without a
risk of breaking DCE 3.1+.

This has been tested for possible regressions on DCE32 HD4550 (RV710).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The SDMA sometimes doesn't seem to work reliable.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org

Mullins is a new CI-based APU.
Signed-off-by: NSamuel Li <samuel.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NChristian König <christian.koenig@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Only VCE 2.0 support so far.

v2: squashing multiple patches into this one
v3: add IRQ support for CIK, major cleanups,
    basic code documentation
v4: remove HAINAN from chipset list
Signed-off-by: NChristian König <christian.koenig@amd.com>

For btc and newer, we may modify the power state depending
on the circumstances.  Use the modified state rather than
the base state.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fill in asic family specific versions rather than
using the generic version.  This lets us handle asic
specific differences more easily.  In this case, we
disable sw swapping of the rtpr writeback value on
r6xx+ since the hw does it for us.  Fixes bogus
rptr readback on BE systems.

v2: remove missed cpu_to_le32(), add comments
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable coarse grained clockgating.  This works properly now
that smc is initialized earlier than the rlc and cp.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable coarse grained clockgating on CIK dGPUs.  This
works properly now that smc is initialized earlier than
the rlc and cp.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Make sure interrupts are enabled
before we enable thermal interrupts.
Also, don't powergate uvd, etc. until after
the ring tests.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Make sure interrupts are enabled
before we enable thermal interrupts.
Also, don't powergate uvd until after
the ring tests.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Make sure interrupts are enabled
before we enable thermal interrupts.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Need to wait to enable cg and pg until after
ring tests. Also make sure interrupts are enabled
before we enable thermal interrupts.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Need to wait to enable cg and pg until after
ring tests. Also make sure interrupts are enabled
before we enable thermal interrupts.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Make sure interrupts are enabled
before we enable thermal interrupts.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Make sure interrupts are enabled before we enable
thermal interrupts.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

I implemented support for this, but forget to hook
up the callback so the driver can actually use it.
On asics with a dedicated DMA engine, we use the DMA
engine for buffer migration so this is just for testing
purposes.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fixes crashes when handling atif events due to the lack of a
callback being registered.
Signed-off-by: NSamuel Li <samuel.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Fill in gpu details for hawaii.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The DMA ring seems to be stable now.

v2: remove pt_ring_index as well
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Uses CP DMA packet just like previous asics.
Useful for debugging and benchmarking.  Uses
same packet format as prior asics.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

When dpm was merged, I added a new asic struct for
rv6xx, but it never got properly updated when the
hdmi callbacks were added due to the two patch sets
being developed in parallel.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=69729Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org

This adds the enable_bapm callback for kb/kv.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds the enable_bapm callback for trinity.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Certain r6xx boards use the same power state for both UVD
and other things.  Since we don't support UVD on r6xx boards
at the moment, there was no callback installed for setting
the UVD clocks, however, on systems that use the same power
state, this leads to a NULL pointer dereference.  Fill
in a stubbed out implementation for now to avoid the crash.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=66963Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: "3.11" <stable@vger.kernel.org>

s/CG/PG/ in the GFX powergating flag name.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Allows you to limit the selected power levels via sysfs.

Force the feedback divider to select a power level.

v2: fix checking in rs780_force_fbdiv,
    drop a duplicate divider structure in rs780_dpm_force_performance_level,
    Force the voltage level too.
Signed-off-by: NAnthoine Bourgeois <anthoine.bourgeois@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Now that the CP is no longer reset and cg is properly
disabled in when appropriate in the dpm code we can
now enable mgcg (medium grained clockgating).
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>