- 13 3月, 2012 1 次提交
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由 Russell King - ARM Linux 提交于
Every DMA engine implementation declares a last completed dma cookie in their private dma channel structures. This is pointless, and forces driver specific code. Move this out into the common dma_chan structure. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk> Tested-by: NLinus Walleij <linus.walleij@linaro.org> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NJassi Brar <jassisinghbrar@gmail.com> [imx-sdma.c & mxs-dma.c] Tested-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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- 02 1月, 2012 1 次提交
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由 Kristen Carlson Accardi 提交于
Drivers should not support both legacy pm and new framework. Signed-off-by: NKristen Carlson Accardi <kristen@linux.intel.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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- 27 10月, 2011 1 次提交
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由 Vinod Koul 提交于
fixup usage of dma direction by introducing dma_transfer_direction, this patch moves dma/drivers/* to use new enum Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Mika Westerberg <mika.westerberg@iki.fi> Cc: H Hartley Sweeten <hartleys@visionengravers.com> Cc: Li Yang <leoli@freescale.com> Cc: Zhang Wei <zw@zh-kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Yong Wang <yong.y.wang@intel.com> Cc: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com> Cc: Boojin Kim <boojin.kim@samsung.com> Cc: Barry Song <Baohua.Song@csr.com> Acked-by: NMika Westerberg <mika.westerberg@iki.fi> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NViresh Kumar <viresh.kumar@st.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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- 31 3月, 2011 1 次提交
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由 Lucas De Marchi 提交于
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: NLucas De Marchi <lucas.demarchi@profusion.mobi>
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- 08 10月, 2010 3 次提交
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由 Koul, Vinod 提交于
In 2.6.36 kernel, dma slave control command was introduced, this patch changes the intel-mid-dma driver to this new kernel slave interface Signed-off-by: NVinod Koul <vinod.koul@intel.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Ramesh Babu K V 提交于
For a very high speed DMA various periphral devices need scatter-gather list support. The DMA hardware support link list items. This list can be circular also (adding new flag DMA_PREP_CIRCULAR_LIST) Right now this flag is in driver header and should be moved to dmaengine header file eventually Signed-off-by: NRamesh Babu K V <ramesh.b.k.v@intel.com> Signed-off-by: NVinod Koul <vinod.koul@intel.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Koul, Vinod 提交于
This patch adds runtime PM support in this dma driver for 4 PCI Controllers Whenever the driver is idle (no channels grabbed), it can go to low power state It also adds the PCI suspend and resume support Signed-off-by: NVinod Koul <vinod.koul@intel.com> Signed-off-by: NAlan Cox <alan@linux.intel.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 28 7月, 2010 1 次提交
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由 Vinod Koul 提交于
This patch add DMA drivers for DMA controllers in Langwell chipset of Intel(R) Moorestown platform and DMA controllers in Penwell of Intel(R) Medfield platfrom This patch adds support for Moorestown DMAC1 and DMAC2 controllers. It also add support for Medfiled GP DMA and DMAC1 controllers. These controllers supports memory to peripheral and peripheral to memory transfers. It support only single block transfers. This driver is based on Kernel DMA engine Anyone who wishes to use this controller should use DMA engine APIs This controller exposes DMA_SLAVE capabilities and notifies the client drivers of DMA transaction completion Config option required to be enabled CONFIG_INTEL_MID_DMAC=y Signed-off-by: NVinod Koul <vinod.koul@intel.com> Signed-off-by: NAlan Cox <alan@linux.intel.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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