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  1. 21 8月, 2015 1 次提交
  3. 01 8月, 2015 1 次提交
  5. 30 7月, 2015 2 次提交
  7. 23 6月, 2015 1 次提交
  9. 22 6月, 2015 2 次提交
  11. 28 5月, 2015 1 次提交
  13. 01 4月, 2015 1 次提交
    • K
      IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers · 5f7f0317
      由 Kevin Cernekee 提交于 
      This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:

 - 64 to 160+ level IRQs
 - Atomic set/clear registers
 - Reasonably predictable register layout (N status words, then N
   mask status words, then N mask set words, then N mask clear words)
 - SMP affinity supported on most systems
 - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3

This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block.  Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.

The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead.  So this driver is primarily intended for MIPS STB chips.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5f7f0317
  15. 15 3月, 2015 1 次提交
  17. 08 3月, 2015 1 次提交
    • S
      irqchip: vf610-mscm-ir: Add support for Vybrid MSCM interrupt router · 0494e11a
      由 Stefan Agner 提交于 
      This adds support for Vybrid's interrupt router. On VF6xx models,
almost all peripherals can be used by either of the two CPU's,
the Cortex-A5 or the Cortex-M4. The interrupt router routes the
peripheral interrupts to the configured CPU.

This IRQ chip driver configures the interrupt router to route
the requested interrupt to the CPU the kernel is running on.
The driver makes use of the irqdomain hierarchy support. The
parent is given by the device tree. This should be one of the
two possible parents either ARM GIC or the ARM NVIC interrupt
controller. The latter is currently not yet supported.

Note that there is no resource control mechnism implemented to
avoid concurrent access of the same peripheral. The user needs
to make sure to use device trees which assign the peripherals
orthogonally. However, this driver warns the user in case the
interrupt is already configured for the other CPU. This provides
a poor man's resource controller.
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>
Link: https://lkml.kernel.org/r/1425249689-32354-2-git-send-email-stefan@agner.chSigned-off-by: NJason Cooper <jason@lakedaemon.net>
      0494e11a
  19. 04 3月, 2015 1 次提交
  21. 26 1月, 2015 1 次提交
  23. 26 11月, 2014 3 次提交
  25. 24 11月, 2014 1 次提交
  27. 09 11月, 2014 1 次提交
  29. 17 9月, 2014 1 次提交
  31. 14 9月, 2014 1 次提交
  33. 20 8月, 2014 1 次提交
  35. 18 8月, 2014 1 次提交
  37. 17 7月, 2014 1 次提交
  39. 09 7月, 2014 2 次提交
  41. 01 7月, 2014 1 次提交
  43. 27 5月, 2014 1 次提交
  45. 26 3月, 2014 1 次提交
  47. 04 3月, 2014 1 次提交
  49. 01 3月, 2014 1 次提交
  51. 05 2月, 2014 1 次提交
    • S
      DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP · 96ca848e
      由 Sricharan R 提交于 
      Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSBAR
that provides flexibility in muxing the device requests to the controller
inputs.

This driver takes care a allocating a free irq and then configuring the
crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
be called right before the irqchip_init, so that it is setup to handle the
irqchip callbacks.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion)
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
      96ca848e
  53. 23 1月, 2014 1 次提交
  55. 15 1月, 2014 2 次提交
  57. 13 12月, 2013 1 次提交
  59. 26 11月, 2013 1 次提交
  61. 24 8月, 2013 1 次提交
  63. 21 8月, 2013 1 次提交
    • J
      irq-imgpdc: add ImgTec PDC irqchip driver · b6ef9161
      由 James Hogan 提交于 
      Add irqchip driver for the ImgTec PowerDown Controller (PDC) as found in
the TZ1090. The PDC has a number of general system wakeup (SysWake)
interrupts (which would for example be connected to a power button or an
external peripheral), and a number of peripheral interrupts which can
also wake the system but are connected straight to specific low-power
peripherals (such as RTC or Infrared). It has a single interrupt output
for SysWakes, and individual interrupt outputs for each peripheral.

The driver demuxes the SysWake interrupt line, and passes the peripheral
interrupts straight through. It also handles the set_wake interrupt
operation to enable/disable the appropriate wake event bits.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: linux-metag@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
      b6ef9161
  65. 05 7月, 2013 1 次提交
  67. 26 6月, 2013 1 次提交