- 25 5月, 2017 1 次提交
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由 Andreas Färber 提交于
Zidoo is a Chinese manufacturer of TV boxes. Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NRob Herring <robh@kernel.org> Acked-by: NRoc He <hepeng@zidoo.tv> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 11 5月, 2017 1 次提交
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由 Christophe Leroy 提交于
This patch updates the binding documentation in accordance with commit 44dd1828 ("mtd: nand: gpio: make nCE GPIO optional") Signed-off-by: NChristophe Leroy <christophe.leroy@c-s.fr> Reported-by: NBrian Norris <computersforpeace@gmail.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 09 5月, 2017 1 次提交
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由 Nicholas Piggin 提交于
The ibm,powerpc-cpu-features device tree binding describes CPU features with ASCII names and extensible compatibility, privilege, and enablement metadata that allows improved flexibility and compatibility with new hardware. The interface is described in detail in ibm,powerpc-cpu-features.txt in this patch. Currently this code is not enabled by default, and there are no released firmwares that provide the binding. Signed-off-by: NNicholas Piggin <npiggin@gmail.com> Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
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- 03 5月, 2017 1 次提交
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由 Christophe Leroy 提交于
This patch allows the use of IRQ to notify the change of GPIO status on MPC8xx CPM IO ports. This then allows to associate IRQs to GPIOs in the Device Tree. Ex: CPM1_PIO_C: gpio-controller@960 { #gpio-cells = <2>; compatible = "fsl,cpm1-pario-bank-c"; reg = <0x960 0x10>; fsl,cpm1-gpio-irq-mask = <0x0fff>; interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>; interrupt-parent = <&CPM_PIC>; gpio-controller; }; The property 'fsl,cpm1-gpio-irq-mask' defines which of the 16 GPIOs have the associated interrupts defined in the 'interrupts' property. Signed-off-by: NChristophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: NScott Wood <oss@buserror.net>
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- 02 5月, 2017 1 次提交
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由 Ludovic Barre 提交于
This patch adds documentation of device tree bindings for the STM32 QSPI controller. Signed-off-by: NLudovic Barre <ludovic.barre@st.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 01 5月, 2017 1 次提交
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由 Quentin Schulz 提交于
The X-Powers AXP20X and AXP22X PMICs can have a battery as power supply. This patch adds the DT binding documentation for the battery power supply which gets various data from the PMIC, such as the battery status (charging, discharging, full, dead), current max limit, current current, battery capacity (in percentage), voltage max and min limits, current voltage and battery capacity (in Ah). Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com> Acked-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NRob Herring <robh@kernel.org> Acked-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk>
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- 29 4月, 2017 1 次提交
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由 Viresh Kumar 提交于
The power-domain provider's #power-domain-cells field is set to 0 and yet the children is using an index to point the power domain. Fix it by removing the index field. Fixes: 70bb510e (dt/bindings / PM/Domains: Update binding for PM domain idle states) Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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- 28 4月, 2017 3 次提交
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由 Kishon Vijay Abraham I 提交于
Update device tree binding documentation of TI's dra7xx PCI controller to include property for enabling unaligned mem access. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Kishon Vijay Abraham I 提交于
Add device tree binding documentation for PCI dra7xx EP mode. Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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由 Kishon Vijay Abraham I 提交于
Add device tree binding documentation for PCI designware EP mode. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NRob Herring <robh@kernel.org>
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- 27 4月, 2017 13 次提交
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由 Icenowy Zheng 提交于
AXP803 have the most regulators in currently supported AXP PMICs. Add info for the regulators in the dt-bindings document. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Icenowy Zheng 提交于
AXP803 is a PMIC produced by Shenzhen X-Powers, with either I2C or RSB bus. Add a compatible for it. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Acked-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Icenowy Zheng 提交于
In the binding documentation of AXP20X mfd, the compatible strings used to be listed for three per line, which leads to some mess when trying to add AXP803 compatible string (as we have already AXP806 and AXP809 compatibles, which is after AXP803 in ascending order). Make the compatible strings one per line, so that inserting a new compatible string will be directly a new line. Signed-off-by: NIcenowy Zheng <icenowy@aosc.io> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Marek Szyprowski 提交于
Exynos LPASS requires some clocks to be enabled to make any access to its registers. This patch adds code for handling such clocks. For current set of registers it is enough to keep sfr0_ctrl clock enabled. Till now it worked only because those clocks were enabled by bootloader and driver probe() happened before they were disabled by clock core because of lack of users. Handling those clocks is also needed to make it possible to enable support for audio power domain. This patch requires adding sfr0_ctrl clock to device tree. Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org> Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: NRob Herring <robh@kernel.org> Acked-for-MFD-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Marek Szyprowski 提交于
Pad retention should be controlled from pin control driver, so remove it from Exynos LPASS driver. After this change, no more access to PMU regmap is needed, so remove also the code for handling PMU regmap. Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Acked-by: NKrzysztof Kozlowski <krzk@kernel.org> Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: NRob Herring <robh@kernel.org> Acked-for-MFD-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Quentin Schulz 提交于
This patch removes the sun4i touchscreen controller binding documentation since it has been merged with the sun4i GPADC binding documentation. Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com> Acked-by: NRob Herring <robh@kernel.org> Acked-by: NDmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Quentin Schulz 提交于
This patch adds documentation for the A33 GPADC binding. Signed-off-by: NQuentin Schulz <quentin.schulz@free-electrons.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Steve Twiss 提交于
Extend existing DA9062 binding information to include the DA9061 PMIC for MFD core and regulators. Add a da9062-onkey link to the existing onkey binding file. Add a da9062-thermal link to the new temperature monitoring binding file. Delete the da9062-watchdog section and replace it with a link to the new DA9061/62 binding information file. Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NSteve Twiss <stwiss.opensource@diasemi.com> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Sean Wang 提交于
This patch adds description for LED as the sub-module on MT6397/MT6323 multifunction device. Signed-off-by: NSean Wang <sean.wang@mediatek.com> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Thor Thayer 提交于
This patch adds documentation for the Altera A10-SR Reset Controller DT bindings. Signed-off-by: NThor Thayer <thor.thayer@linux.intel.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Milo Kim 提交于
This patch describes overall binding for TI LMU MFD devices. Signed-off-by: NMilo Kim <milo.kim@ti.com> Acked-by: NRob Herring <robh+dt@kernel.org> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Rask Ingemann Lambertsen 提交于
commit b101829a029a ("mfd: axp20x: Fix AXP806 access errors on cold boot") was intended to fix the case where a board uses an AXP806 in slave mode, but the boot loader leaves it in master mode for lack of AXP806 support. But now the driver breaks on boards where the PMIC is operating in master mode. To let the device tree describe which mode of operation is needed, this patch introduces a new property "xpowers,master-mode". Fixes: 204ae296 ("mfd: axp20x: Add bindings for AXP806 PMIC") Signed-off-by: NRask Ingemann Lambertsen <rask@formelder.dk> Acked-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Florian Fainelli 提交于
The described GPIO reset property is applicable to *all* child PHYs. If we have one reset line per PHY present on the MDIO bus, these automatically become properties of the child PHY nodes. Finally, indicate how the RESET pulse width must be defined, which is the maximum value of all individual PHYs RESET pulse widths determined by reading their datasheets. Fixes: 69226896 ("mdio_bus: Issue GPIO RESET to PHYs.") Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Reviewed-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 26 4月, 2017 2 次提交
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由 olivier moysan 提交于
This patch adds documentation of device tree bindings for the STM32 SAI ASoC driver. Signed-off-by: Nolivier moysan <olivier.moysan@st.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 John Hsu 提交于
Add driver for NAU88L24. Signed-off-by: NJohn Hsu <KCHSU0@nuvoton.com> Signed-off-by: NJohn Hsu <supercraig0719@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 25 4月, 2017 15 次提交
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由 Leif Middelschulte 提交于
This patch implements consideration of the SPI_READY mode flag as defined in spi.h. It extends the device tree bindings to support the values defined by the reference manual for the DRCTL field. Thus supporting edge-triggered and level-triggered bursts. Signed-off-by: NLeif Middelschulte <Leif.Middelschulte@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Masahiro Yamada 提交于
The driver sets appropriate DMA mask. Delete the "dma-mask" DT property. See [1] for negative comments for this binding. [1] https://lkml.org/lkml/2016/2/8/57Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
There are various customizable parameters, so several variants for this IP. A generic compatible like "denali,denali-nand-dt" is useless. Moreover, there are multiple things wrong with this string. (Refer to Rob's comment [1]) The "denali,denali-nand-dt" was added by Altera for the SOCFPGA port. Replace it with a more specific string "altr,socfpga-denali-nand". There are no users (in upstream) of the old compatible string. The Denali IP on SOCFPGA incorporates the hardware ECC fixup engine. So, this capability should be associated with the compatible. [1] https://lkml.org/lkml/2016/12/1/450Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Boris Brezillon 提交于
The old NAND bindings were not exactly describing the hardware topology and were preventing definitions of several NAND chips under the same NAND controller. New bindings address these limitations and should be preferred over the old ones for new SoCs/boards. Old bindings are still supported for backward compatibility but are marked deprecated in the doc. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: NNicolas Ferre <nicolas.ferre@microchip.com> Acked-by: NRob Herring <robh@kernel.org>
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由 Olimpiu Dejeu 提交于
Signed-off-by: NOlimpiu Dejeu <olimpiu@arcticsand.com> Acked-by: NRob Herring <robh@kernel.org> Acked-by: NDaniel Thompson <daniel.thompson@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Hu Ziji 提交于
Marvell Xenon SDHC can support eMMC/SD/SDIO. Add Xenon-specific properties. Also add properties for Xenon PHY setting. Signed-off-by: NHu Ziji <huziji@marvell.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Jan Glauber 提交于
Add description of Cavium Octeon and ThunderX SOC device tree bindings. CC: Ulf Hansson <ulf.hansson@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> CC: devicetree@vger.kernel.org Signed-off-by: NJan Glauber <jglauber@cavium.com> Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NSteven J. Hill <steven.hill@cavium.com> Acked-by: NRob Herring <robh+dt@kernel.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Sergio Prado 提交于
Adds the device tree bindings description for Samsung S3C24XX MMC/SD/SDIO controller, used as a connectivity interface with external MMC, SD and SDIO storage mediums. Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NSergio Prado <sergio.prado@e-labworks.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Piotr Sroka 提交于
DTS properties are used instead of fixed data because PHY settings can be different for different chips/boards. Add description of new DLL PHY delays. Signed-off-by: NPiotr Sroka <piotrs@cadence.com> Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 yong mao 提交于
Add description for mediatek,hs200-cmd-int-delay Add description for mediatek,hs400-cmd-int-delay Add description for mediatek,hs400-cmd-resp-sel-rising Signed-off-by: NYong Mao <yong.mao@mediatek.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chris Brandt 提交于
Signed-off-by: NChris Brandt <chris.brandt@renesas.com> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Eric Anholt 提交于
This is the other SD controller on the platform, which can be swapped to the role of SD card host using pin muxing. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NGerd Hoffmann <kraxel@redhat.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Thierry Reding 提交于
The SDHCI controller found on Tegra186 in very similar to the controller found on earlier generations of Tegra. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Thierry Reding 提交于
The list of compatible strings is somewhat difficult to read and extend. Reformat it into a list to make it more easily extensible. While at it, also remove the "plus one of the above" clause because it isn't actually valid. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Roger Quadros 提交于
Some boards [1] leave the PHYs at an invalid state during system power-up or reset thus causing unreliability issues with the PHY which manifests as PHY not being detected or link not functional. To fix this, these PHYs need to be RESET via a GPIO connected to the PHY's RESET pin. Some boards have a single GPIO controlling the PHY RESET pin of all PHYs on the bus whereas some others have separate GPIOs controlling individual PHY RESETs. In both cases, the RESET de-assertion cannot be done in the PHY driver as the PHY will not probe till its reset is de-asserted. So do the RESET de-assertion in the MDIO bus driver. [1] - am572x-idk, am571x-idk, a437x-idk Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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