- 07 10月, 2011 1 次提交
-
-
由 Mark Salter 提交于
The C6X SoCs contain several PLL controllers each with up to 16 clock outputs feeding into the cores or peripheral clock domains. The hardware is very similar to arm/mach-davinci clocks. This is still a work in progress which needs to be updated once device tree clock binding changes shake out. Signed-off-by: NMark Salter <msalter@redhat.com> Signed-off-by: NAurelien Jacquiot <a-jacquiot@ti.com> Acked-by: NArnd Bergmann <arnd@arndb.de>
-